ADP3152

–11–

REV. 0

Board Layout Guidelines

1. The power loop should be routed on the PCB to encompass

small areas to minimize radiated switching noise energy to

the control circuit and thus to avoid circuit problems caused

by noise. This technique also helps to reduce radiated EMI.

The power loop includes the input capacitors, the two

MOSFETs, the sense resistor, the inductor, and the output

capacitors. The ground terminals of the input capacitors, the

low side FET, the ADP3152, and the output capacitors

should be connected together with short and wide traces. It is

best to use an internal ground plane.

2. The PGND (power ground) pin of the ADP3152 must re-

turn to the grounded terminals of the input and output ca-

pacitors and to the source of the low side MOSFET with the

shortest and widest traces possible. The AGND (analog

ground) pin has to be connected to the ground terminals of

the timing capacitor and the compensating capacitor, again

with the shortest leads possible, and before it is connected to

the PGND pin.

3. The positive terminal of the input capacitors must be con-

nected to the drain of the high side MOSFET. The source

terminal of this FET is connected to the drain of the low side

FET, (whose source is connected to the ground plane direct)

with the widest and shortest traces possible. To kill parasitic

ringing at the input of the buck inductor due to parasitic

capacitances and inductances, a small (L >3 mm) ferrite

bead is recommended to be placed in the drain lead of the

low side FET. Also, to minimize dissipation of the high side

FET, a low voltage 1 A Schottky diode can be connected

between the input of the buck inductor and the source of the

low side FET.

4. The positive terminal of the bypass capacitors of the +12 V

with the shortest leads possible. The negative terminals must

be connected to the PGND pin of the ADP3152.

5. The sense pins of the ADP3152 must be connected to the

sense resistor with as short traces as possible. Make sure that

the two sense traces are routed together with minimum sepa-

ration (<1 mm). The output side of the sense resistor should

(Each square unit of 1 ounce Cu-trace has a resistance of

~0.53 m

Ω. At 14 A, each mΩ of PCB trace resistance be-

the CPU will reduce the regulated output voltage by 14 mV.

The filter capacitors to ground at the sense terminals of the

IC should be as close as possible (<8 mm) to the ADP3152.

The common ground of the optional filter capacitors should

be connected to the AGND pin of the ADP3152 with the

shortest traces possible (<10 mm).

6. The microprocessor load should be connected to the output

terminals of the converter with the widest and shortest traces

possible. Use overlapping traces in different layers to mini-

mize interconnection inductance.