ADP3152 datasheet(9/12 Pages) AD

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ADP3152

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The minimum input voltage dictates whether standard threshold

or logic-level threshold MOSFETs must be used. For VIN > 8 V,

standard threshold MOSFETs (VGS(TH) < 4 V) may be used. If

VIN is expected to drop below 8 V, logic-level threshold MOSFETs

(VGS(TH) < 2.5 V) are strongly recommended. Only logic-level

MOSFETs with VGS ratings higher than the absolute maximum

of VCC should be used.

The maximum output current IOMAX determines the RDS(ON)

requirement for the two power MOSFETs. When the ADP3152

is operating in continuous mode, the simplifying assumption can

be made that one of the two MOSFETs is always conducting

the average load current.

For VIN = 5 V and VO = 2.8 V, the maximum duty ratio of the

high side FET is:

DMAXHF = (1–fMIN

× t

OFF) =(1–160 kHz

× 2.2 µs) = 65%

The maximum duty ratio of the low side (synchronous rectifier)

FET is:

DMAXLF = 1 – DMAXHF = 35%

The maximum rms current of the high side FET is:

IRMSLS = [DMAXHF (ILVALLEY

2 + I

LPEAK

2 + I

LVALLEYILPEAK)/3]

0.5

= 11.5 Arms

The maximum rms current of the low side FET is:

IRMSLS = [DMAXLF (ILVALLEY

2 + I

LPEAK

2 + I

LVALLEYILPEAK)/3]

0.5

= 8.41 Arms

The RDS(ON) for each FET can be derived from the allowable

dissipation. If we allow 5% of the maximum output power for

FET dissipation, the total dissipation will be:

PFETALL = 0.05 VOIOMAX = 2 W

Allocating two-thirds of the total dissipation for the high side

FET and one-third for the low side FET, the required minimum

FET resistances will be:

RDS(ON)HSF(MIN) = 1.33/11.5

2 = 10 m

Ω

RDS(ON)LSF(MIN) = 0.67/8.41

2 = 9.5 m

Ω

Note that there is a tradeoff between converter efficiency and

cost. Larger FETs reduce the conduction losses and allow higher

efficiency but lead to increased cost. If efficiency is not a major

concern the Fairchild MOSFET NDP6030L or International

Rectifier IRL3103 is an economical choice for both the high side

and low side positions. Those devices have an RDS(ON) of 14 m

Ω

at VGS = 10 V and at 25

°C. The low side FET is turned on with

at least 10 V. The high side FET, however, is turned on with

only 12 V – 5 V = 7 V. If we check the typical output character-

istics of the device in the data sheet, we find that for an output

current of 10 A, and at a VGS of 7 V, the VDS is 0.15 V, which

gives a RDS(ON) = VDS/ID = 15 m

Ω. This value is only slightly

above the one specified at a VGS of 10 V, so the resistance in-

crease due to the reduced gate drive can be neglected. We have

to modify, however, the specified RDS(ON) at the expected high-

est FET junction temperature of 140

°C by a R

DS(ON) multiplier,

using the graph in the data sheet. In our case:

RDS(ON)MULT = 1.7

Using this multiplier, the expected RDS(ON) at 140

°C is 1.7 × 14

= 24 m

Ω.

The high side FET dissipation is:

PDFETHS = IRMSHS

DS(ON) + 0.5 VINILPEAKQGfMAX/IG = 3.72 W

where the second term represents the turn-off loss of the FET.

(In the second term, QG is the gate charge to be removed from

the gate for turn-off and IG is the gate current. From the data

sheet, QG is about 50 nC –70 nC and the gate drive current

provided by the ADP3152 is about 1 A.)

The low side FET dissipation is:

PDFETLS = IRMSLS

DS(ON) = 1.7 W

(Note that there are no switching losses in the low side FET.)

To remove the dissipation of the chosen FETs, proper heatsinks

should be used. The Thermalloy 6030 heatsink has a thermal

impedance of 13

°C/W with convection cooling. With this heat-

sink, the junction-to-ambient thermal impedance of the chosen

high side FET

JAHS will be 13 (heatsink-to-ambient) + 2 (junc-

tion-to-case) + 0.5 (case-to-heatsink) = 15.5

°C/W.

At full load and at 50

°C ambient temperature, the junction

temperature of the high side FET is:

TJHSMAX = TA + θJAHS PDFETHS = 105°C

A smaller heatsink may be used for the low side FET, e.g., the

Thermalloy type 7141 (

θ = 20.3°C/W). With this heatsink, the

thermal impedance

JALS for the low side FET = 33.8

°C/W.

The low side FET junction temperature is:

TJLSMAX = TA + θJALS PDFETLS = 106°C

All of the above calculated junction temperatures are safely

below the 175

°C maximum specified junction temperature of

the selected FET.

The maximum operating junction temperature of the ADP3152

is calculated as follows:

TJICMAX = TA + θJA (IICVCC + PDR)

where

JA is the junction to ambient thermal impedance of the

ADP3152 and PDR is the drive power. From the data sheet,

is equal to 110

°C/W and I

IC = 2.7 mA. PDR can be calculated as

follows:

PDR = (CRSS + CISS)VCC

2 f

MAX = 307 mW

The result is:

TJICMAX = 86°C

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