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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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ADC912AFP bảng dữ liệu(PDF) 3 Page - Analog Devices |
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ADC912AFP bảng dữ liệu(HTML) 3 Page - Analog Devices |
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3 / 16 page  REV. B ADC912A –3– t CONV t 6 t 7 DATA OUTPUTS READ D11 D10 D9 D8 D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 t 1 t 2 t 3 t 5 t 1 t 10 OLD DATA DB11 – DB0 NEW DATA DB11 – DB0 CS RD BUSY DATA Figure 5. Parallel Read Timing Diagram, Slow-Memory Mode (HBEN = LOW) CS RD BUSY DATA HBEN DATA OUTPUTS FIRST READ SECOND READ D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 LOW LOW LOW LOW DB11 DB10 DB9 DB8 t 8 t 1 t 2 t 3 t CONV t 6 t 7 t 5 t 9 t 8 t 1 t 10 t 3 t 7 t 5 t 9 t 4 NEW DATA DB7 – DB0 NEW DATA DB11 – DB8 OLD DATA DB7 – DB0 Figure 6. Two-Byte Read Timing Diagram, Slow-Memory Mode TIMING CHARACTERISTICS1, 2 (V DD = +5 V 5%, VSS = –11.4 V to –15.75 V, VREFIN = –5 V, Analog Input 0 V to 10 V; External fCLK = 1.25 MHz; –40 C to +85 C applies to ADC912A/F unless otherwise noted. See Figures 5 to 8.) Parameter Symbol Conditions Min Typ Max Unit CS to RD Setup Time t1 0ns RD to BUSY Propagation Delay t2 150 ns Data Access Time after READ t3 3 CL = 100 pF 65 125 ns Read Pulsewidth t4 3 90 ns CS to RD Hold Time t5 0ns New Data Valid after BUSY t6 3 CL = 100 pF –30 0 ns Bus Disconnect Time t7 20 60 90 ns HBEN to RD Setup Time t8 20 ns HBEN to RD Hold Time t9 20 ns Delay between Successive Read Operations t10 350 250 ns NOTES 1Guaranteed by design. 2All input control signals are specified with t R = tF = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 3t 3, t4, and t6 are measured with the load circuits of Figure 3 and timed for and output to cross 0.8 V or 2.4 V. 4t 7 is the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 4. Specifications subject to change without notice. TIMING DIAGRAMS CS RD BUSY DATA t 1 t 2 t 3 t 7 t 3 t 7 t CONV t 5 t 1 t 2 t CONV t 5 t 4 NEW DATA DB11 – DB0 OLD DATA DB11 – DB0 DATA OUTPUTS D11 D10 D9 D8 D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 FIRST READ (OLD DATA) SECOND READ DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 t 4 Figure 7. Parallel Read Timing Diagram, ROM Mode (HBEN = LOW) DATA OUTPUTS D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8 FIRST READ (OLD DATA) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SECOND READ LOW LOW LOW LOW DB11 DB10 DB9 DB8 THIRD READ DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 t 8 t 1 t 2 t 3 t 7 t 4 t 9 t 5 t 8 t 1 t 3 t 4 t 9 t 10 t 3 t 7 t 2 t 4 t 1 t 5 t 8 t 9 t 7 t 5 CS RD BUSY DATA HBEN NEW DATA DB7 – DB0 NEW DATA DB11 – DB8 OLD DATA DB7 – DB0 t CONV Figure 8. Two-Byte Read Timing Diagram, ROM Mode |
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