EM47DM0888SBA datasheet(5/39 Pages) EOREX

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EM47DM0888SBA

May. 2011

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Pin Description (Simplified)

Name

Function

F7,G7

CK, CK

(System Clock)

CK and CK are differential clock inputs. All address and control

input signals are sampled on the crossing of the positive edge of

CK and negative edge of CK . Output (read) data is referenced to

the crossings of CK and CK (both directions of crossing).

(Chip Select)

All commands are masked when CS is registered HIGH.

CS provides for external Rank selection on systems with

multiple Ranks. CS is considered part of the command code.

CKE

(Clock Enable)

CKE high activates and CKE low deactivates internal clock

signals and device input buffers and output drivers. Taking CKE

low provides precharge power-down and self- refresh operation

(all banks idle), or active power-down (row active in any bank).

CKE is asynchronous for self refresh exit. After VREFCA has

become stable during the power on and initialization sequence, it

must be maintained during all operations (including self-refresh).

CKE must be maintained high throughout read and write

accesses. Input buffers, excluding CK, CK , ODT and CKE are

disabled during power-down. Input buffers, excluding CKE, are

disabled during self -refresh.

K3,L7,L3,K2,

L8,L2,M8,M2,

N8,M3,H7,M7,

K7,N3

A0~A9,A10/AP,

A11,A12( BC ),

A13

(Address)

Provided the row address (RA0 – RA13) for active commands

and the column address (CA0-CA9) and auto precharge bit for

read/write commands to select one location out of the memory

array in the respective bank. A10 is sampled during a precharge

command to determine whether the precharge applies to one

bank (A10 LOW) or all banks (A10 HIGH). The address inputs

also provide the op-code during Mode Register Set commands.

A12 is sampled during read and write commands to determine if

burst chop (on-the-fly) will be performed. (HIGH: no burst chop,

LOW: burst chopped). See command truth table for details.

J2,K8,J3

BA0, BA1,BA2

(Bank Address)

BA0 – BA2 define to which bank an active, read, write or

precharge command is being applied. Bank address also

determines if the mode register is to be accessed during a MRS

cycle.

ODT

(On Die Termination)

ODT (registered HIGH) enables termination resistance internal to

the DDR3 SDRAM. When enabled, ODT is applied to each DQ,

DQS, DQS , DM/TDQS, and TDQS signal. The ODT pin will be

ignored if the Mode Register MR1 is programmed to disable ODT.

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