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EM47DM0888SBA bảng dữ liệu(PDF) 34 Page - Eorex Corporation

tên linh kiện EM47DM0888SBA
Giải thích chi tiết về linh kiện  JEDEC Standard VDD/VDDQ
PDF  39 Pages
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nhà sản xuất  EOREX [Eorex Corporation]
Trang chủ  http://www.eorex.com
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Mode Register MR1
The Mode Register MR1 stores the data for enabling or disabling the DLL, output driver strength, RTT_Nom
impedance, additive latency, write leveling enable, TDQS enable and Qoff. The Mode Register 1 is written by
asserting low on /CS, /RAS, /CAS, /WE, high on BA0, low on BA1 and BA2, while controlling the states of
address pins according to the table below.
DLL
D.I.C
Rtt
AL
D.I.C
Rtt
Level
0
Rtt
0
TDQS
Qoff
0
0 1
0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
BA0
BA1
BA2
1
Disable
0
Enable
A0
DLL Enable
1
1
Reserved
0
1
RZQ/5
1
0
RZQ/7
0
0
RZQ/6
A1
A5
Output Driver
Impedance Control
1
1
1
Reserved
0
1
1
Reserved
1
0
1
RZQ/8
0
0
1
RZQ/12
1
1
0
RZQ/6
0
1
0
RZQ/2
1
0
0
RZQ/4
0
0
0
ODT disabled
A2
A6
A9
Rtt_Nom
1
Enabled
0
Disabled
A11
TDQS enable
1
Output buffer disabled
0
Output buffer enabled
A12
Qoff
1
1
Reserved
0
1
CL - 2
1
0
CL - 1
0
0
0
A3
A4
Additive Latency
1
Enabled
0
Disabled
A8
Write leveling enable
1
1
MR3
0
1
MR2
1
0
MR1
0
0
MR0
BA0
BA1
MRS Mode
DLL
D.I.C
Rtt
AL
D.I.C
Rtt
Level
0
Rtt
0
TDQS
Qoff
0
0 1
0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
BA0
BA1
BA2
1
Disable
0
Enable
A0
DLL Enable
1
1
Reserved
0
1
RZQ/5
1
0
RZQ/7
0
0
RZQ/6
A1
A5
Output Driver
Impedance Control
1
1
1
Reserved
0
1
1
Reserved
1
0
1
RZQ/8
0
0
1
RZQ/12
1
1
0
RZQ/6
0
1
0
RZQ/2
1
0
0
RZQ/4
0
0
0
ODT disabled
A2
A6
A9
Rtt_Nom
1
Enabled
0
Disabled
A11
TDQS enable
1
Output buffer disabled
0
Output buffer enabled
A12
Qoff
1
1
Reserved
0
1
CL - 2
1
0
CL - 1
0
0
0
A3
A4
Additive Latency
1
Enabled
0
Disabled
A8
Write leveling enable
1
1
MR3
0
1
MR2
1
0
MR1
0
0
MR0
BA0
BA1
MRS Mode
Note1.
BA2, A8, A10 and A13 are reserved for future use (RFU) and must be programmed to 0 during MRS.
Note2.
Qoff: Outputs disabled - DQs, DQSs, /DQSs.
Note3.
In Write leveling Mode (MR1[bit7] = 1) with MR1[bit12] = 1, all RTT_Nom settings are allowed; in Write
Leveling Mode (MR1[bit7] = 1) with MR1[bit12] = 0, only RTT_Nom settings of RZQ/2, RZQ/4 and
RZQ/6 are allowed.
Note4.
New RON value is defined as RON48=RZQ/5.



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