MMA955xL

Sensors

Freescale Semiconductor, Inc.

7

3

General Description

3.1

Functional Overview

The MMA955xL device consists of a 3-axis, MEMS accelerometer and a mixed-signal ASIC with an integrated, 32-bit CPU. The

mixed-signal ASIC can be utilized to measure and condition the outputs of the MEMS accelerometer, internal temperature sensor,

or a differential analog signal from an external device.

Figure 1. Platform block diagram(1)

1. Preliminary data for memory sizes.

A block level view of is shown in the preceding figure and can be summarized at a high level as an analog/mixed-mode subsystem

associated with a digital engine:

• The analog sub-system is composed of:

– A 3-axis transducer that is an entirely passive block including the MEMS structures.

– An Analog Front End (AFE) with the following:

• A capacitance-to-voltage converter (C to V)

• An analog-to-digital converter

• A temperature sensor

• The digital sub-system is composed of:

– The 32-bit, ColdFire V1 CPU with a Background-Debug Module (BDM)

– Memory: RAM, ROM, and flash

– Rapid GPIO (RGPIO) port-control logic

– Timer functions include:

• Modulo timer module (MTIM16)

• Programmable Delay Timer (PDB)

Analog Front End (AFE)

BDM

INTC

DBG

4 KB x 32

Flash

1 KB x 32

ROM

512 KB x 32

RAM

I

X

axis

C to V

ADC

Temp

Sensor

I

SPI slave

Control

and

mailbox

CLKGEN

Two-channel, 16-bit

Timer / PWM module

16-bit

Modulo timer module

Programmable

delay block

INT_ O

Y

axis

Z

axis

RESET

SCL0/RGPIC0/SCLK

SDA0/RGPIO1/SDI

RGPIO2/SCL1/SDO

RGPIO3/SDA1/SSB

RGPIO4/INT

RGPIO5/PDB_A/INT_O

RGPIO6/AN0/TPMCH0

RGPIO7/AN1/TPMCH1

RGPIO8/PDB_B

BKGD/MS/RPGPIO9

AN0

AN1

TPMCH0

TPMCH1

SCL1

SCL0

PDB_A

PDB_B

SCLK

SDI

SDO

SSB

SCL0

SDA0

BKGD

INT

V1

ColdFire Core

with MAC