AD8150AST datasheet(14/35 Pages) AD

14 / 35 page

AD8150

–14–

REV. 0

CS INPUT

UPDATE INPUT

ENABLING

OUT[0:16][N:P]

OUTPUTS

DISABLING

OUT[0:16][N:P]

OUTPUTS

WE INPUT

tCSU

tUOT

tUOE

tWOT

tWHU

INPUT {DATA 1}

INPUT {DATA 2}

INPUT {DATA 0}

tCHU

tUW

tWOD

Figure 27. First Rank Write Cycle and Second Rank Update Cycle

Table V. First Rank Write Cycle and Second Rank Update Cycle

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

tCSU

Setup Time

Chip Select to Update

TA = 25

°C0

tCHU

Hold Time

Chip Select from Update

VDD = 5 V

tUOE

Output Enable Times

Update to Output Enable

VCC = 5 V

tWOE*

Write Enable to Output Enable

tUOT

Output Toggle Times

Update to Output Reprogram

tWOT

Write Enable to Output Reprogram

tUOD*

Output Disable Times

Update to Output Disabled

tWOD

Write Enable to Output Disabled

tWHU

Setup Time

Write Enable to Update

tUW

Width of Update Pulse

*Not Shown.

A[4:0]

INPUTS

tCSR

D[6:0]

OUTPUTS

tRDE

tAA

tRHA

CS INPUT

RE INPUT

ADDR 1

ADDR 2

DATA

{ADDR1}

DATA {ADDR2}

tCHR

tRDD

Figure 28. Second Rank Readback Cycle

Table VI. Second Rank Readback Cycle

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

tCSR

Setup Time

Chip Select to Read Enable

TA = 25

°C0

tCHR

Hold Time

Chip Select from Read Enable

VDD = 5 V

tRHA

Address from Read Enable

VCC = 5 V

tRDE

Enable Time

Data from Read Enable

10 k

Ω

tAA

Access Time

Data from Address

20 pF on D[6:0]

tRDD

Release Time

Data from Read Enable

Bus

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