AD8150AST datasheet(13/35 Pages) AD

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AD8150

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Control Interface Timing Diagrams

CS INPUT

tASW

tAHW

tDSW

WE INPUT

A[4:0] INPUTS

D[6:0] INPUTS

tCSW

tWP

tCHW

tDHW

Figure 25. First Rank Write Cycle

Table III. First Rank Write Cycle

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

tCSW

Setup Time

Chip Select to Write Enable

TA = 25

°C0

tASW

Address to Write Enable

VDD = 5 V

tDSW

Data to Write Enable

VCC = 5 V

tCHW

Hold Time

Chip Select from Write Enable

tAHW

Address from Write Enable

tDHW

Data from Write Enable

tWP

Width of Write Enable Pulse

PREVIOUS RANK 2 DATA

CS INPUT

UPDATE INPUT

ENABLING

OUT[0:16][N:P]

OUTPUTS

TOGGLE

OUT[0:16][N:P]

OUTPUTS

DISABLING

OUT[0:16][N:P]

OUTPUTS

DATA FROM RANK 1

tCSU

tUOE

tCHU

DATA FROM RANK 1

DATA FROM RANK 2

tUW

tUOD

tUOT

Figure 26. Second Rank Update Cycle

Table IV. Second Rank Update Cycle

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

tCSU

Setup Time

Chip Select to Update

TA = 25

°C0

tCHU

Hold Time

Chip Select from Update

VDD = 5 V

tUOE

Output Enable Times

Update to Output Enable

VCC = 5 V

tUOT

Output Toggle Times

Update to Output Reprogram

tUOD

Output Disable Times

Update to Output Disabled

tUW

Width of Update Pulse

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