AD7716 datasheet(4/16 Pages) AD

4 / 16 page

REV. A

AD7716

–4–

Limit at TMIN, TMAX

Parameter

(B Version)

Units

Conditions/Comments

fCLKIN

3, 4

400

kHz min

CLKIN Frequency

MHz max

ns max

Digital Output Rise Time. Typically 20 ns

ns max

Digital Output Fall Time. Typically 20 ns

1/fCLKIN

ns min

CASCIN Pulse Width

1/fCLKIN

ns min

CASCIN to DRDY Setup Time

1/2fCLKIN + 30

ns max

DRDY

Low to SCLK Low Delay

t10

ns max

CLKIN High to DRDY Low, SCLK Active, RFS Active

t11

ns max

CLKIN High to SCLK High Delay

t12

ns min

SCLK Width

t13

1/fCLKIN

SCLK Period

t14

ns max

SCLK High to RFS High Delay

t15

1/fCLKIN

RFS

Pulse Width

t16

ns max

SCLK High to SDATA Valid Delay

t17

1/2fCLKIN + 50

ns max

SCLK Low to SDATA High Impedance Delay

1/2fCLKIN + 10

ns min

t18

1/2fCLKIN + 60

ns max

CLKIN High to DRDY High Delay

t19

ns max

CLKIN High to RFS High Impedance, SCLK High Impedance

ns min

t20

1/2fCLKIN + 50

ns max

SCLK Low to CASCOUT High Delay

t21

2/fCLKIN

CASCOUT Pulse Width

NOTES

1Sample tested at +25

°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

2See Figures 1 and 3.

3CLKIN duty cycle range is 40% to 60%.

4The AD7716 is production tested with f

CLKIN at 8 MHz in the slave mode. It is guaranteed by characterization to operate at 400 kHz and 8 MHz in master mode.

5Specified using 10% and 90% points on waveform of interest.

16 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.

17 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated

back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish

time of the part and as such is independent of external bus loading capacitances.

MASTER MODE TIMING CHARACTERISTICS1, 2 (AV

DD = DVDD = +5 V

5%; AVSS = –5 V

5%; AGND = DGND = 0 V;

fCLKIN = 8 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DVDD; unless otherwise noted)

Figure 3. Master Mode Timing Diagram

DB31

CH1

CASCIN (I)

SCLK (O)

RFS (O)

SDATA (O)

CASCOUT (O)

DB30

CH1

DB29

CH1

DB25

CH1

DB24

CH1

DB23

CH1

DB2

CH4

DB1

CH4

DB0

CH4

CLKIN (I)

DRDY (O)

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