AD7716 datasheet(3/16 Pages) AD

3 / 16 page

REV. A

–3–

AD7716

Table I. Typical Usable Dynamic Range, RMS Noise and Filter Settling Time vs. Filter Cutoff Frequency

Programmed Cutoff

Output Update

Usable Dynamic

RMS Noise

Filter Settling Time to

Absolute Group

Frequency (Hz)

Rate (Hz)

Range (dB)

( V)

0.0007% FS (ms)

Delay (ms)

584

2232

1.35

0.675

292

1116

102

2.7

1.35

146

558

105

5.4

2.7

279

108

10.8

5.4

36.5

140

111

21.6

10.8

NOTE

Usable Dynamic Range is defined as the ratio of the rms full-scale reading (sine wave input) to the rms noise of the converter.

CONTROL REGISTER TIMING CHARACTERISTICS1, 2 (AV

DD = DVDD = +5 V

5%; AVSS = –5 V

5%; AGND =

DGND = 0 V; fCLKIN = 8 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DVDD; unless otherwise noted)

Limit at TMIN, TMAX

Parameter

(B Version)

Units

Conditions/Comments

1/fCLKIN

ns min

SCLK Period

ns min

SCLK Width

ns min

TFS

Setup Time

ns min

SDATA Setup Time

ns min

SDATA Hold Time

ns min

TFS

Hold Time

NOTES

1Sample tested at +25

°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

2See Figure 2.

3CLKIN Duty Cycle range is 40% to 60%.

200

µA

IOH

+2.1V

OUTPUT

1.6mA

50pF

IOL

Figure 1. Load Circuit for Access Time and Bus Relinquish Time

DB4

(DB12)

DB3

(DB11)

DB2

(DB10)

DB1

(DB9)

DB0

(DB8)

DB5

(DB13)

DB6

(DB14)

DB7

(DB15)

SCLK (I)

SDATA (I)

TFS (I)

Figure 2. Control Register Timing Diagram

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