AD7713 datasheet(3/28 Pages) AD

3 / 28 page

Parameter

A, S Versions1

Units

Conditions/Comments

REFERENCE INPUT

REF IN(+) – REF IN(–) Voltage

+2.5 to AVDD/1.8

V min to V max

For Specified Performance. Part Is Functional with Lower

VREF Voltages

Input Sampling Rate, fS

fCLK IN/512

Normal-Mode 50 Hz Rejection

100

dB min

For Filter Notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, 50 Hz,

±0.02 × f

NOTCH

Normal-Mode 60 Hz Rejection6

100

dB min

For Filter Notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, 60 Hz,

±0.02 × f

NOTCH

Common-Mode Rejection (CMR)

100

dB min

At DC

Common-Mode 50 Hz Rejection6

150

dB min

For Filter Notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, 50 Hz,

±0.02 × f

NOTCH

Common-Mode 60 Hz Rejection

150

dB min

For Filter Notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, 60 Hz,

±0.02 × f

NOTCH

Common-Mode Voltage Range10

AGND to AVDD

V min to V max

DC Input Leakage Current @ +25

°C

pA max

TMIN to TMAX

nA max

LOGIC INPUTS

Input Current

±10

µA max

All Inputs Except MCLK IN

VINL, Input Low Voltage

0.8

V max

VINH, Input High Voltage

2.0

V min

MCLK IN Only

VINL, Input Low Voltage

0.8

V max

VINH, Input High Voltage

3.5

V min

LOGIC OUTPUTS

VOL, Output Low Voltage

0.4

V max

ISINK = 1.6 mA

VOH, Output High Voltage

4.0

V min

ISOURCE = 100 µA

Floating State Leakage Current

±10

µA max

Floating State Output Capacitance

pF typ

TRANSDUCER BURN-OUT

Current

µA nom

Initial Tolerance @ +25

°C

±10

% typ

Drift

0.1

°C typ

RTD EXCITATION CURRENTS

(RTD1, RTD2)

Output Current

200

µA nom

Initial Tolerance @ +25

°C

±20

% max

Drift

ppm/

°C typ

Initial Matching @ +25

°C

±1

% max

Matching Between RTD1 and RTD2 Currents

Drift Matching

ppm/

°C typ

Matching Between RTD1 and RTD2 Current Drift

Line Regulation (AVDD)

200

nA/V max

AVDD = +5 V

Load Regulation

200

nA/V max

SYSTEM CALIBRATION

AIN1, AIN2

Positive Full-Scale Calibration Limit

+(1.05

× V

REF)/GAIN

V max

GAIN Is the Selected PGA Gain (Between 1 and 128)

Negative Full-Scale Calibration Limit

–(1.05

× V

REF)/GAIN

V max

GAIN Is the Selected PGA Gain (Between 1 and 128)

Offset Calibration Limit14, 15

–(1.05

× V

REF)/GAIN

V max

GAIN Is the Selected PGA Gain (Between 1 and 128)

Input Span

+0.8

× V

REF/GAIN

V min

GAIN Is the Selected PGA Gain (Between 1 and 128)

+(2.1

× V

REF)/GAIN

V max

GAIN Is the Selected PGA Gain (Between 1 and 128)

AIN3

Positive Full-Scale Calibration Limit

+(4.2

× V

REF)/GAIN

V max

GAIN Is the Selected PGA Gain (Between 1 and 128)

Offset Calibration Limit

0 to VREF/GAIN

V max

GAIN Is the Selected PGA Gain (Between 1 and 128)

Input Span

+3.2

× V

REF/GAIN

V min

GAIN Is the Selected PGA Gain (Between 1 and 128)

+(4.2

× V

REF)/GAIN

V max

GAIN Is the Selected PGA Gain (Between 1 and 128)

NOTES

12Guaranteed by design, not production tested.

13After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, then the device will

output all 0s.

14These calibration and span limits apply provided the absolute voltage on the AIN1 and AIN2 analog inputs does not exceed AV

DD + 30 mV or go more negative

than AGND – 30 mV.

15The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.

AD7713

–3–

REV. C

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