AD7302 datasheet(3/16 Pages) AD

tên linh kiện	AD7302

Giải thích chi tiết về linh kiện	2.7 V to 5.5 V, Parallel Input Dual Voltage Output 8-Bit DAC

PDF	16 Pages

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AD7302

–3–

REV. 0

TIMING CHARACTERISTICS1, 2

Limit at TMIN, TMAX

Parameter

(B Version)

Units

Conditions/Comments

ns min

Address to Write Setup Time

ns min

Address Valid to Write Hold Time

ns min

Chip Select to Write Setup Time

ns min

Chip Select to Write Hold Time

ns min

Write Pulse Width

ns min

Data Setup Time

4.5

ns min

Data Hold Time

ns min

Write to

LDAC Setup Time

ns min

LDAC Pulse Width

t10

ns min

CLR Pulse Width

NOTES

1Sample tested at +25

°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V

DD) and timed from a voltage level of

(VIL + VIH)/2. tr and tf should not exceed 1 µs on any digital input.

2See Figure 1.

A/B

D7–D0

LDAC

CLR

t10

Figure 1. Timing Diagram for Parallel Data Write

(VDD = +2.7 V to +5.5 V; GND = 0 V; Reference = Internal VDD/2 Reference;

all specifications TMIN to TMAX unless otherwise noted)

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