AD6432AST datasheet(16/20 Pages) AD

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AD6432

–16–

REV. 0

Evaluation Board Description

This four layer board demonstrates both the transmit and

receive functions of the AD6432. The top internal layer is a

ground plane and the bottom internal layer is a strategically

partitioned power plane with DUT power and bipolar support

device power.

A 20-pin Berg strip connector provides the external power and

dc signal interface, which includes power-up, gain and external

reference bias options. The various high frequency IF, LO, TX

Modulation output (MODO) and the Demodulator Reference

(FREF) are brought in and out of the board via end-launch

SMA connectors. Appropriate terminations are provided for

each signal. Several hardware jumpers are provided for bias and

IF selection options. Figure 36 shows the placement of the

different connectors used on the evaluation board.

FREF

MODO

LOINP

OPTLO

RFHI

J23

J25

J24

J26

J21

AD6432 EVAL.

REV. B

MXOP

IFIP

J22

Figure 36. Evaluation Board Layout (Top View)

Note: MXOP, IFHI, OPTLO are optional SMA connectors not

supplied with the evaluation board.

Interface Connector (Berg Strip) Pin Description

Building up a simple IDC connector/ribbon cable breakout to a

vector board or box with banana plugs will facilitate testing.

Figure 37 shows the signal’s placement and Table II describes

each signal.

BOARD

EDGE

Figure 37. Evaluation Board Interface Connector

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