AD6432AST datasheet(11/20 Pages) AD

11 / 20 page

AD6432

–11–

REV. 0

PRODUCT OVERVIEW

The AD6432 provides most of the active circuitry required to

realize a complete low power, single-conversion superhetero-

dyne time division transceiver, or the latter part of a double-

conversion transceiver, at input receive frequencies up to

350 MHz with an IF from 10 MHz to 50 MHz and transmit

frequencies up to 300 MHz. The internal I/Q demodulators,

with their associated phase-locked loop and the internal I/Q

modulator, support a wide variety of modulation modes, includ-

ing n-PSK, n-QAM, and GMSK. A single positive supply volt-

age of 3 V is required (2.7 V minimum, 3.6 V maximum) at a

typical supply current of 13 mA at midgain in receive mode and

13 mA in transmit mode. In the following discussion, VPOS will

be used to denote the power supply voltage, which will be as-

sumed to be 3 V.

RFHI

RFLO

MXOP

MXOM

BANDPASS

FILTER

IFIP

IFIM

3MHz

4.7k

Ω

4.7k

Ω

4.7k

Ω

4.7k

Ω

DIVIDE BY

1 OR 2

PHASE

DETECTOR

GAIN TEMP. COMPENSATION

LOHI

LOLO

MODO

PCAO

IRXN

IRXP

QRXN

QRXP

IFS0

FREF

FLTR

GAIN

GREF

RXPU

TXPU

ITXN

ITXP

QTXN

QTXP

PCAP

PCAM

QUADRATURE

VCO

RX, TX

BIAS

AD6432

Figure 27. Functional Block Diagram

Figure 27 shows the main sections of the AD6432. In the re-

ceive path, it consists of a variable-gain UHF mixer and linear

two-stage IF strip, both of which together provide a calibrated

voltage-controlled gain range of more than 80 dB, followed by a

tunable IF bandpass filter and dual quadrature demodulators.

These are driven by inphase and quadrature clocks generated

by a Phase-Locked Loop (PLL) locked to a corrected external

reference. In the transmit path it consists of a quadrature modu-

lator followed by a low-pass filter. The quadrature modulator is

driven by quadrature frequencies that are generated internally

by dividing the external local oscillator frequency by two. A

CMOS-compatible power-down interface completes the AD6432.

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