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AD6426 Data Sheet Change Summary

June 10, 1998

Page

1 of 2

AD6426 Preliminary Revision 2.3

(Changes from Revision 1.0)

Number

Date

Description of Change

5/19/98

Motorola Serial Display mode added.

5/19/98

TXENABLE NMI function freeing up the IRQ6 pin added.

5/19/98

Dimensional tolerances for BGA package outline drawing added.

5/19/98

Memory I/F timing specs separated into characteristics and requirements.

5/19/98

Dual band control signals renamed- BANDSELECT0 is multiplexed with GPIO[2], BANDSELECT1

is multiplexed with GPIO[1]. For DB radios requiring a single Bandselect bit, BANDSELECT0 is

enabled. For DB radios requiring 2 Bandselect bits then both BANSELECT0,1 can be enabled.

These signals were previously referred to as BANDSELECT and DCSSEL.

5/19/98

VBC and radio I/F diagram in Figure 6 updated to show a generic DB radio I/F.

5/19/98

DAI I/F Pins updated to be consistent with DAI Box users manual.

5/19/98

GPIO[7:0] Pin functions in Mode D (Table 24) were incorrectly listed as being all Tristate outputs.

The correct function is GPIO7 = TRI and GPIO[6:0] = O.

5/20/98

Requirements for 32kHz crystal for slow clocking added.

5/20/98

Pin functions in Emulation mode GPO 0,6,7 in Table 24 are renamed to reserve.

5/20/98

Memory Interface Timing Specification: read timing specs changed to max with the exception of

Control Processor data hold and Parameters broken out separately into requirements and

characteristics.

6/9/98

In Fig 24 the following pins were incorrectly labeled and thus changed;

a) Pin 45 from HWR to UBS

b) Pin 46 from LWR to LBS

c) Pin 98 from GND to VDD

d) Pin 99 from VDD to GND

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