CY8C56LP datasheet(5/120 Pages) CYPRESS

5 / 120 page

PRELIMINARY

PSoC® 5LP: CY8C56LP Family

Datasheet

Document Number: 001-84935 Rev. **

Page 5 of 120

very low power internal low-speed oscillator (ILO) for the sleep

and watchdog timers. A 32.768-kHz external watch crystal is

also supported for use in RTC applications. The clocks, together

with programmable clock dividers, provide the flexibility to

integrate most timing requirements.

The CY8C56LP family supports a wide supply operating range

from 1.71 to 5.5 V. This allows operation from regulated supplies

such as 1.8 ± 5%, 2.5 V ±10%, 3.3 V ± 10%, or 5.0 V ± 10%, or

directly from a wide range of battery types. In addition, it provides

an integrated high efficiency synchronous boost converter that

can power the device from supply voltages as low as 0.5 V. This

enables the device to be powered directly from a single battery.

In addition, you can use the boost converter to generate other

voltages required by the device, such as a 3.3 V supply for LCD

glass drive. The boost’s output is available on the VBOOST pin,

allowing other devices in the application to be powered from the

PSoC.

PSoC supports a wide range of low power modes. These include

a 300 nA hibernate mode with RAM retention and a 2 µA sleep

mode with RTC. In the second mode the optional 32.768-kHz

watch crystal runs continuously and maintains an accurate RTC.

Power to all major functional blocks, including the programmable

digital and analog peripherals, can be controlled independently

by firmware. This allows low power background processing

when some peripherals are not in use. This, in turn, provides a

total device current of only 3.1 mA when the CPU is running at

6MHz.

The details of the PSoC power modes are covered in the “Power

System” section on page 24 of this datasheet.

PSoC uses JTAG (4 wire) or SWD (2 wire) interfaces for

programming, debug, and test. Using these standard interfaces

you can debug or program the PSoC with a variety of hardware

solutions from Cypress or third party vendors. The Cortex-M3

debug and trace modules include Flash Patch and Breakpoint

(FPB), Data Watchpoint and Trace (DWT), Embedded Trace

Macrocell (ETM), and Instrumentation Trace Macrocell (ITM).

These modules have many features to help solve difficult debug

and trace problems. Details of the programming, test, and

debugging interfaces are discussed in the “Programming, Debug

Interfaces, Resources” section on page 57 of this datasheet.

2. Pinouts

Each VDDIO pin powers a specific set of I/O pins. (The USBIOs

are powered from VDDD.) Using the VDDIO pins, a single PSoC

can support multiple voltage levels, reducing the need for

off-chip level shifters. The black lines drawn on the pinout

diagrams in Figure 2-3 and Figure 2-4 show the pins that are

Each VDDIO may source up to 100 mA total to its associated I/O

pins, as shown in Figure 2-1.

Figure 2-1. VDDIO Current Limit

Conversely, for the 100-pin and 68-pin devices, the set of I/O

pins associated with any VDDIO may sink up to 100 mA total, as

shown in Figure 2-2.

Figure 2-2. I/O Pins Current Limit

PSoC

VDDIO X

IDDIO X = 100 mA

I/O Pins

PSoC

VDDIO X

Ipins = 100 mA

I/O Pins

VSSD

Note

4. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.

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