CY8C56LP datasheet(4/120 Pages) CYPRESS

4 / 120 page

PRELIMINARY

PSoC® 5LP: CY8C56LP Family

Datasheet

Document Number: 001-84935 Rev. **

Page 4 of 120

For more details on the peripherals see the “Example

Peripherals” section on page 35 of this datasheet. For

information on UDBs, DSI, and other digital blocks, see the

“Digital Subsystem” section on page 34 of this datasheet.

PSoC’s analog subsystem is the second half of its unique

configurability. All analog performance is based on a highly

accurate absolute voltage reference with less than 0.1% error

over temperature and voltage. The configurable analog

subsystem includes:

Analog muxes

Comparators

Analog mixers

Voltage references

ADCs

DACs

DFB

All GPIO pins can route analog signals into and out of the device

using the internal analog bus. This allows the device to interface

up to 62 discrete analog signals.

Some CY8C56LP devices offer a fast, accurate, configurable

delta-sigma ADC with these features:

Less than 100 µV offset

A gain error of 0.2 percent

INL less than ±1 LSB

DNL less than ±1 LSB

SINAD better than 66 dB

The CY8C56LP family also offers one or two successive

approximation register (SAR) ADCs, depending on device

selected. Featuring 12-bit conversions at up to 1 M samples per

second, they also offer low nonlinearity and offset errors and

SNR better than 70 dB. They are well suited for a variety of

higher speed analog applications.

The output of either ADC can optionally feed the programmable

DFB via DMA without CPU intervention. You can configure the

DFB to perform IIR and FIR digital filters and several user

defined custom functions. The DFB can implement filters with up

to 64 taps. It can perform a 48-bit multiply-accumulate (MAC)

operation in one clock cycle.

Four high speed voltage or current DACs support 8-bit output

signals at an update rate of up to 8 Msps. They can be routed

out of any GPIO pin. You can create higher resolution voltage

PWM DAC outputs using the UDB array. This can be used to

create a pulse width modulated (PWM) DAC of up to 10 bits, at

up to 48 kHz. The digital DACs in each UDB support PWM, PRS,

or delta-sigma algorithms with programmable widths.

In addition to the ADCs, DACs, and DFB, the analog subsystem

provides multiple:

Comparators

Uncommitted opamps

Configurable switched capacitor/continuous time (SC/CT)

blocks. These support:

Transimpedance amplifiers

Programmable gain amplifiers

Mixers

Other similar analog components

See the “Analog Subsystem” section on page 46 of this

datasheet for more details.

PSoC’s CPU subsystem is built around a 32-bit three-stage

pipelined ARM Cortex-M3 processor running at up to 67 MHz.

The Cortex-M3 includes a tightly integrated nested vectored

interrupt controller (NVIC) and various debug and trace modules.

The overall CPU subsystem includes a DMA controller, flash

cache, and RAM. The NVIC provides low latency, nested

interrupts, and tail-chaining of interrupts and other features to

increase the efficiency of interrupt handling. The DMA controller

enables peripherals to exchange data without CPU involvement.

This allows the CPU to run slower (saving power) or use those

CPU cycles to improve the performance of firmware algorithms.

The flash cache also reduces system power consumption by

allowing less frequent flash access.

PSoC’s nonvolatile subsystem consists of flash, byte-writeable

EEPROM, and nonvolatile configuration options. It provides up

to 256 KB of on-chip flash. The CPU can reprogram individual

blocks of flash, enabling boot loaders. You can enable an ECC

for high reliability applications. A powerful and flexible protection

model secures the user's sensitive information, allowing

selective memory block locking for read and write protection.

Two KB of byte-writable EEPROM is available on-chip to store

application data. Additionally, selected configuration options

such as boot speed and pin drive mode are stored in nonvolatile

memory. This allows settings to activate immediately after power

on reset (POR).

The three types of PSoC I/O are extremely flexible. All I/Os have

many drive modes that are set at POR. PSoC also provides up

to four I/O voltage domains through the VDDIO pins. Every GPIO

has analog I/O, LCD drive, CapSense, flexible interrupt

generation, slew rate control, and digital I/O capability. The SIOs

on PSoC allow VOH to be set independently of VDDIO when used

as outputs. When SIOs are in input mode they are high

impedance. This is true even when the device is not powered or

when the pin voltage goes above the supply voltage. This makes

the SIO ideally suited for use on an I2C bus where the PSoC may

not be powered when other devices on the bus are. The SIO pins

also have high current sink capability for applications such as

LED drives. The programmable input threshold feature of the

SIO can be used to make the SIO function as a general purpose

analog comparator. For devices with FS USB the USB physical

interface is also provided (USBIO). When not using USB these

pins may also be used for limited digital functionality and device

programming. All the features of the PSoC I/Os are covered in

detail in the “I/O System and Routing” section on page 28 of this

datasheet.

The PSoC device incorporates flexible internal clock generators,

designed for high stability and factory trimmed for high accuracy.

The Internal Main Oscillator (IMO) is the master clock base for

the system, and has 1% accuracy at 3 MHz. The IMO can be

configured to run from 3 MHz up to 62 MHz. Multiple clock

derivatives can be generated from the main clock frequency to

meet application needs. The device provides a PLL to generate

system clock frequencies up to 67 MHz from the IMO, external

crystal, or external reference clock. It also contains a separate,

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