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PXD10PB bảng dữ liệu(PDF) 16 Page - Freescale Semiconductor, Inc

tên linh kiện PXD10PB
Giải thích chi tiết về linh kiện  32-bit Power Architecture짰 Microcontrollers for Entry Level Display Solutions
PDF  26 Pages
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

PXD10PB bảng dữ liệu(HTML) 16 Page - Freescale Semiconductor, Inc

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PXD10 Product Brief, Rev. 1
Features
Freescale Semiconductor
16
— Autonomous LIN frame handling
— Message buffer to store identifier and up to eight data bytes
— Supports message length of up to 64 bytes
— Detection and flagging of LIN errors
— Sync field; Delimiter; ID parity; Bit, Framing; Checksum and Timeout errors
— Classic or extended checksum calculation
— Configurable Break duration of up to 36-bit times
— Programmable Baud rate prescalers (13-bit mantissa, 4-bit fractional)
— Diagnostic features
– Loop back
–Self Test
– LIN bus stuck dominant detection
— Interrupt driven operation with 16 interrupt sources
— LIN slave mode features
– Autonomous LIN header handling
– Autonomous LIN response handling
– Discarding of irrelevant LIN responses using up to 16 ID filters
2.4.15
Serial Peripheral Interface (SPI) module
The SPI modules provide a synchronous serial interface for communication between the PXD10 MCU and
external devices.
The SPI features the following:
•
Up to two SPI modules
•
Full duplex, synchronous transfers
•
Master or slave operation
•
Programmable master bit rates
•
Programmable clock polarity and phase
•
End-of-transmission interrupt flag
•
Programmable transfer baud rate
•
Programmable data frames from 4 to 16 bits
•
Up to 6 chip select lines available, depending on package and pin multiplexing, enable 64 external
devices to be selected using external muxing from a single SPI
•
8 clock and transfer attributes registers
•
Chip select strobe available as alternate function on one of the chip select pins for deglitching
•
FIFOs for buffering up to 4 transfers on the transmit and receive side
•
General purpose I/O functionality on pins when not used for SPI
•
Queueing operation possible through use of eDMA



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