WM8224 datasheet(19/50 Pages) WOLFSON

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WM8224

Production Data

PD, Rev 4.1, June 2012

RESET LEVEL CLAMPING (RLC)

To ensure that the signal applied to the WM8224 lies within the supply voltage range (0V to AVDD)

the output signal from a CCD is usually level shifted by coupling through a capacitor, CIN. The RLC

circuit clamps the WM8224 side of this capacitor to a suitable voltage through a CMOS switch during

the CCD reset period (pixel clamping) or during the black pixels (line clamping). In order for clamping

to produce correct results the input voltage during the clamping must be a constant value.

Note that if the ac coupling capacitor (CIN) is used in non-CDS mode (CDS=0), then to minimise code

drift, line clamping should be used and internal input voltage buffers enabled using the FOL_EN

should be used, and the voltage buffers need not be enabled.

The WM8224 allows the user to control the RLC switch in a variety of ways as illustrated in Figure 13.

This figure shows a single channel, however all 3 channels are identical, each with its own clamp

switch controlled by the common CLMP signal.

The method of control chosen depends upon the characteristics of the input video. The RLCEN

default RLCEN=1).

Note that unused inputs should be left floating, or grounded through a decoupling capacitor, if reset

level clamping is used.

Figure 13 RLC Clamp Control Options

When an input waveform has a stable reference level on every pixel it may be desirable to clamp

every pixel during this period. Setting CLMPCTRL=0 means that the RLC switch is closed whenever

the RSMP input pin is high, as shown in Figure 14.

MCLK

VSMP

RSMP

RLC switch control

"CLMP"

(RLCEN=1,CLMPCTRL=0)

RLC switch closed

when RSMP=1

Video sample taken on

fallling edge of VSMP

Reset/reference sample taken

on fallling edge of RSMP

INPUT VIDEO

SIGNAL

reference

("black") level

video level

Figure 14 Reset Level Clamp Operation (CLMPCTRL=0), CDS operation shown, non-CDS also possible

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