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WM8961 bảng dữ liệu(PDF) 97 Page - Wolfson Microelectronics plc |
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WM8961 bảng dữ liệu(HTML) 97 Page - Wolfson Microelectronics plc |
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97 / 116 page ![]() WM8961 Pre-Production w PP, August 2009, Rev 3.1 97 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R68 (44h) Analogue PGA Bias 2:0 HP_PGAS_BIAS[2:0] 011 Headphone PGA bias options 000 x 2 001 Reserved 010 Reserved 011 x 1 100-111 Reserved Register 44h Analogue PGA Bias REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R69 (45h) Analogue HP 0 7 HPL_RMV_SHORT 0 Left channel output short removal: set after output stage has been enabled 6 HPL_ENA_OUTP 0 Enables left channel output stage; set after offset cancellation is done 5 HPL_ENA_DLY 0 delayed left channel enable, set with at least 20us delay to HPL_ENA; reset together with HPL_ENA 4 HPL_ENA 0 enables left headphone amplifier. Channel 3 HPR_RMV_SHORT 0 right channel output short removal: set after output stage has been enabled 2 HPR_ENA_OUTP 0 enables right channel output stage; set after offset cancellation is done 1 HPR_ENA_DLY 0 delayed right channel enable, set with at least 20us delay to HPR_ENA; reset together with HPR_ENA 0 HPR_ENA 0 enables right headphone amplifier. Channel Register 45h Analogue HP 0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R72 (48h) Charge Pump 1 0 CP_ENA 0 Enable charge-pump digits 0: disable 1: enable Register 48h Charge Pump 1 |
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