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WM8961 bảng dữ liệu(PDF) 55 Page - Wolfson Microelectronics plc

tên linh kiện WM8961
Giải thích chi tiết về linh kiện  Ultra-Low Power Stereo CODEC with 1W Stereo Class D Speaker Drivers and Ground Referenced Headphone Drivers
PDF  116 Pages
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nhà sản xuất  WOLFSON [Wolfson Microelectronics plc]
Trang chủ  http://www.wolfsonmicro.com
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WM8961 bảng dữ liệu(HTML) 55 Page - Wolfson Microelectronics plc

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WM8961
Pre-Production
w
PP, August 2009, Rev 3.1
55
DC SERVO CONFIGURATION FOLLOWING A HEADPHONE PGA VOLUME
UPDATE
When a PGA volume update is applied to the headphone output, its DC offset can change. To
maintain sub 1.5mV DC offsets, it may be necessary to re-calibrate the DC correction factors when
large changes are made to PGA settings in the signal path (6dB or greater). The DC Servo can be
configured to do this automatically as a background task using the DCS_TRIG_SERIES_HPL/R. This
function is not handled by the write control sequencer since it can happen at any time and is not part
of a defined sequence.
This function is only available on the headphone outputs since it is not required for inputs.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R61 (3Dh)
DC Servo 1
4
DCS_TRIG_SERIES_HPL
0
0= do not perform any series of updates on HPL
1= Perform a DCS_SERIES_NO_HP series of LSB
updates on channel HPL *see note 1
One channel completes before the next starts
Reading this register returns status of this task.
Read
0 = task completed.
1 = task being performed
0
DCS_TRIG_SERIES_HPR
0
0= do not perform any series of updates on HPR
1= Perform a DCS_SERIES_NO_HP series of LSB
updates on channel HPR *see note 1
One channel completes before the next starts
Reading this register returns status of this task.
Read
0 = task completed.
1 = task being performed
Table 38 DC Servo Series Updates following Volume Update
Note:
1.
These bits are automatically reset to ‘0’ after 1 clock cycle.
The DCS_TRIG_SERIES_X will update the channel a “number of times” before moving onto the next
enabled channel. The “number of times” it updates a particular channel, is configured by
DCS_SERIES_NO_HP.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R65 (41h)
DC Servo 5
6:0
DCS_SERIES_NO_HP[6:0]
001_0000
Number of LSB updates in a series for channels HPL
and HPR
000_0000-000_1111 : Reserved
001_0000 : 16
…
111_1111 : 127
Table 39 DC Servo Number of Updates Control
After any large gain update and volume updates have completed, the DCS_TRIG_SERIES_X bit
should be set. The DC Servo will then examine each enabled output in order and apply any required
offset correction to each.
To prevent any audible artifacts on the analogue outputs, the DC Servo only applies any necessary
corrections in discreet 0.25mV steps. To allow this correction during audio playback, the DC Servo
includes a high order, low pass filter which removes any AC signal content from each output before it
measures the DC offset. This filter has a relatively long time constant which means that the servo will
take approx 0.275 seconds for each 0.25mV correction on each enabled analogue channel. This
means that the DC Servo may remain active, in the background, for several seconds after the
DCS_TRIG_SERIES_X bit is set. Refer to “DC Servo Filter Bandwidth” section for more information.



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