WM8533 datasheet(13/41 Pages) WOLFSON

tên linh kiện	WM8533

Giải thích chi tiết về linh kiện	24-bit 192kHz Stereo DAC with 2Vrms Ground Referenced Line Output

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Production Data

WM8533

PD, July 2012, Rev 4.0

POWER ON RESET

Figure 6 Internal Power on Reset Circuit Schematic

The WM8533 includes an internal Power-On-Reset circuit, as shown in Figure 6, which is used to

reset the DAC digital logic into a default state after power up. The POR circuit is powered by AVDD

and has as its inputs VMID and LINEVDD. It asserts POR low if VMID or LINEVDD are below a

minimum threshold.

Figure 7 Typical Power Timing Requirements

Figure 7 shows a typical power-up sequence where LINEVDD comes up with AVDD. When AVDD

goes above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee POR is

asserted low and the chip is held in reset. In this condition, all writes to the control interface are

ignored. After VMID rises to Vpord_hi and AVDD rises to Vpora_hi, POR is released high and all registers

are in their default state and writes to the control interface may take place.

On power down, POR is asserted low whenever LINEVDD or AVDD drop below the minimum

threshold Vpora_low.

WM8533 bảng dữ liệu(PDF) 13 Page - Wolfson Microelectronics plc