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LPC81XM bảng dữ liệu(PDF) 15 Page - NXP Semiconductors |
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LPC81XM bảng dữ liệu(HTML) 15 Page - NXP Semiconductors |
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15 / 67 page ![]() LPC81xM All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Objective data sheet Rev. 1.0 — 7 November 2012 15 of 67 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 7.9 Switch Matrix (SWM) The switch matrix controls the function of each digital or mixed analog/digital pin in a highly flexible way by allowing to connect many functions like the USART, SPI, SCT, and I2C functions to any pin that is not power or ground. These functions are called movable functions and are listed in Table 4. Functions that need specialized pads like the oscillator pins XTALIN and XTALOUT can be enabled or disabled through the switch matrix. These functions are called fixed-pin functions and cannot move to other pins. The fixed-pin functions are listed in Table 3. If a fixed-pin function is disabled, any other movable function can be assigned to this pin. 7.10 Fast General-Purpose parallel I/O (GPIO) Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs can be set or cleared in one write operation. LPC81xM use accelerated GPIO functions: • GPIO registers are located on the ARM Cortex M0+ IO bus for fastest possible single-cycle I/O timing. Fig 7. Standard I/O pad configuration 3,1 9'' 9'' (6' 966 (6' VWURQJ SXOOXS VWURQJ SXOOGRZQ 9'' ZHDN SXOOXS ZHDN SXOOGRZQ RSHQGUDLQHQDEOH RXWSXWHQDEOH UHSHDWHUPRGH HQDEOH SXOOXSHQDEOH SXOOGRZQHQDEOH VHOHFWGDWD LQYHUWHU GDWDRXWSXW GDWDLQSXW VHOHFWJOLWFK ILOWHU DQDORJLQSXW VHOHFWDQDORJLQSXW DDD SLQFRQILJXUHG DVGLJLWDORXWSXW GULYHU SLQFRQILJXUHG DVGLJLWDOLQSXW SLQFRQILJXUHG DVDQDORJLQSXW 352*5$00$%/( */,7&+),/7(5 |
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