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L99DZ70XP bảng dữ liệu(PDF) 41 Page - STMicroelectronics

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L99DZ70XP
SPI - control and status registers
Doc ID 15162 Rev 3
41/47
5.8
Configuration register
Table 32.
Configuration register (read/write)
Bit
Name
Comment
15
0
Reserved (has to be set to '0')
14
0
13
0
12
0
11
0
10
0
90
80
70
60
5
Mask for bit 15 of
status reg. 1
Openload event (under-current status bit of OUT1 HS) is not
considered in openload bit 1 of global status register.
4
Mask for bit 14 of
status reg. 1
Openload event (under-current status bit of OUT1 LS) is not
considered in openload bit 1 of global status register.
3
Mask for bit 3 of
global status reg.
Temperature warning event is not considered in the 'Global Error
Flag'.
2
0
Reserved (has to be set to '0')
1
Mask for bit 1 of
global status reg.
Openload event (under-current status bit of OUTn) is not considered
in the 'Global Error Flag'.
0
0
Reserved (has to be set to '0')



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