STA369BWS datasheet(30/89 Pages) STMICROELECTRONICS

30 / 89 page

STA369BWS

30/89

Doc ID 16861 Rev 4

To make the STA369BWS work properly, the serial audio interface LRCKI clock must be

synchronous to the PLL output clock. It means that:

N-4< = (frequency of PLL clock) / (frequency of LRCKI) = < N+4 cycles,

where N depends on the settings in Table 12 on page 27.

the PLL must be locked.

If these two conditions are not met, and IDE bit (register 0x05, bit 2) is set to 1, the

STA369BWS immediately mutes the I2S PCM data out (provided to the processing block)

and it freezes any active processing task.

Clock desyncronization can happen during STA369BWS operation because of source

switching or TV channel change. To avoid audio side effects, like click or pop noise, it is

strongly recommended to complete the following actions:

soft volume change

I2C read /write instructions

while the serial audio interface and the internal PLL are still synchronous.

Delay serial clock enable

64 * fs

0000

I2S 24-bit data

0100

I2S 20-bit data

1000

I2S 18-bit data

1100

LSB first I2S 16-bit data

0001

Left-justified 24-bit data

0101

Left-justified 20-bit data

1001

Left-justified 18-bit data

1101

Left-justified 16-bit data

0010

Right-justified 24-bit data

0110

Right-justified 20-bit data

1010

Right-justified 18-bit data

1110

Right-justified 16-bit data

Table 20.

Delay serial clock enable

Bit

R/W

RST

Name

Description

R/W

DSCKE

0: no serial clock delay

1: serial clock delay by 1 core clock cycle to tolerate

anomalies in some I2S master devices

Table 19.

Supported serial audio input formats for LSB-first (SAIFB = 1) (continued)

BICKI

SAI [3:0]

SAIFB

Interface Format

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