STA339BW datasheet(58/77 Pages) STMICROELECTRONICS

58 / 77 page

STA339BW

58/77

Doc ID 15251 Rev 5

6.12.12

Coefficient a2 data register bits 15:8

6.12.13

Coefficient a2 data register bits 7:0

6.12.14

Coefficient b0 data register bits 23:16

6.12.15

Coefficient b0 data register bits 15:8

6.12.16

Coefficient b0 data register bits 7:0

6.12.17

Coefficient write/read control register

Coefficients for user-defined EQ, mixing, scaling, and bass management are handled

internally in the STA339BW via RAM. Access to this RAM is available to the user via an I2C

coefficient base address, five sets of three store the values of the 24-bit coefficients to be

written or that were read, and one contains bits used to control the write/read of the

coefficient(s) to/from RAM.

Three different RAM banks are embedded in STA339BW. The three banks are managed in

paging mode using EQCFG register bits. They can be used to store different EQ settings.

For speaker frequency compensation, a sampling frequency independent EQ must be

implemented. Computing three different coefficients set for 32 kHz, 44.1kHz, 48 kHz and

downloading them into the three RAM banks, it is possible to select the suitable RAM block

depending from the incoming frequency with a simple I2C write operation on register 0x31.

C4B15

C4B14

C4B13

C4B12

C4B11

C4B10

C4B9

C4B8

000

C4B7

C4B6

C4B5

C4B4

C4B3

C4B2

C4B1

C4B0

000

C5B23

C5B22

C5B21

C5B20

C5B19

C5B18

C5B17

C5B16

000

C5B15

C5B14

C5B13

C5B12

C5B11

C5B10

C5B9

C5B8

000

C5B7

C5B6

C5B5

C5B4

C5B3

C5B2

C5B1

C5B0

000

Reserved

000

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