STA333BW datasheet(28/67 Pages) STMICROELECTRONICS

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STA333BW

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Doc ID 13773 Rev 3

Different power devices use different output modes.

FFX compensating pulse size register

Overcurrent warning adjustment bypass

The OCRB is used to indicate how STA333BW behaves when an overcurrent warning

condition occurs. If OCRB = 0 and the overcurrent condition happens, the power control

block forces an adjustment to the modulation limit (default is -3 dB) in an attempt to

eliminate the overcurrent warning condition. Once the overcurrent warning clipping

adjustment is applied, it remains in this state until reset is applied or OCRB is set to 1. The

level of adjustment can be changed via the TWOCL (thermal warning / overcurrent limit)

setting at address 0x37 of the user defined coefficient RAM (Section 6.7.7 on page 54).

The

OCRB can be enabled when the output bridge is already on.

Table 22.

FFX power output mode

Bit

R/W

RST

Name

Description

R/W

OM0

Selects configuration of FFX output:

00: drop compensation

01: discrete output stage: tapered compensation

10: full-power mode

11: variable drop compensation (CSZx bits)

1R/W

OM1

Table 23.

FFX compensating pulse size bits

Bit

R/W

RST

Name

Description

2R/W

CSZ0

When OM[1,0] = 11, this register determines the

size of the FFX compensating pulse from 0 clock

ticks to 15 clock periods.

3R/W

CSZ1

4R/W

CSZ2

5R/W

CSZ3

Table 24.

Compensating pulse size

CSZ[3:0]

Compensating pulse size

0000

0 ns (0 tick) compensating pulse size

0001

20 ns (1 tick) clock period compensating pulse size

……

1111

300 ns (15 tick) clock period compensating pulse size

Table 25.

Overcurrent warning bypass

Bit

R/W

RST

Name

Description

R/W

OCRB

0: overcurrent warning adjustment enabled

1: overcurrent warning adjustment disabled

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