BFS520 datasheet(57/130 Pages) NXP

57 / 130 page

NXP Semiconductors RF Manual 16th edition

2.3.3

VSAT,2-waycommunicationviasatellite

Design a Ku-/ Ka-band VSAT transceiver that meets IESS-308

with NXP's Ku-/ Ka-band RF LO generators

The TFF100xHN family are Ku-band RF PLLs, with integrated VCO intended for low phase-noise local-

oscillator (LO) circuits in Ku- & Ka-band VSAT transmitters and transceivers. Manufactured in a high-

performance SiGe:C process, these devices deliver extremely low phase noise and comply with the IESS-308

from Intelsat.

Features

` Phase noise compliant with IESS-308 (Intelsat)

` Differential input and output

` Divider settings at 16, 32, 64, 128, or 256

` Lock-detect output

` SiGe:C technology (120 GHz f

T process)

` HVQFN24 (SOT616-1) package

Applications

` VSAT block upconverters

` VSAT down conversion

` Local oscillator signal generation

VSAT networks are commonly used to transmit narrowband

data, such as point-of-sale transactions for credit cards, or to

transmit broadband data that supports satellite Internet access

to a remote location, VoIP, or video.

The network typically consists of a dish antenna, an outdoor

unit, and an indoor unit. The outdoor unit is used for

frequency translation between RF and IF, and usually includes

a microwave-based uplink/downlink separator, a low noise

block (LNB) for receiving the downlink signals, and a block

Upconverter (BUC).

The VSAT ICs can be used to create the LO generator for a

linear BUC (meaning the IF or RF conversion is done by mixing

with an LO).

To enable precise frequency and time multiplexing, the

downlink signal provides an accurate frequency reference of

10 MHz. The indoor unit frequency multiplexes this with the

uplink IF signal, and the LO signal in the BUC needs to be

frequency-locked to the reference.

The TFF100xHN ICs are housed in a 24-pin HVQFN (SOT616-1)

package. The pins have been assigned for optimal performance.

Three voltage domains are used to separate the block on the

IC, and two pins for each output (OUT-P and OUT-N) have been

reserved to match a typical layout using a linewidth of Z = 50 Ω

microstrip on a 20-mil RO4003 board (1.1 mm).

The ground pins have been placed next to the reference input

and the output, and, to minimize crossings in the application,

all the supply pins are on the same side of the IC.

BFS520 bảng dữ liệu(PDF) 57 Page - NXP Semiconductors

BFS520 bảng dữ liệu(HTML) 57 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL