TM4EP72BPB, TM4EP72BJB, 4194304 BY 72BIT

TM4EP72CPB, TM4EP72CJB 4194304 BY 72BIT

EXTENDEDDATAOUT BUFFERED DYNAMIC RAM MODULES

SMMS686A − AUGUST 1997 − REVISED FEBRUARY 1998

9

POST OFFICE BOX 1443

ac timing requirements (see Note 3)

’4EP72xxB-50

’4EP72xxB-60

’4EP72xxB-70

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

tRC

Cycle time, random read or write

84

104

124

ns

tRWC

Cycle time, read-write

116

140

165

ns

tRASP

Pulse duration, RASx active, fast page mode (see Note 6)

50

100 000

60

100 000

70

100 000

ns

tRAS

Pulse duration, RASx active, non-page mode (see Note 6)

50

10 000

60

10 000

70

10 000

ns

tRP

Pulse duration, RASx precharge

30

40

50

ns

tWP

Pulse duration, write command

9

11

11

ns

tASC

Setup time, column address

0

0

0

ns

tASR

Setup time, row address

5

5

5

ns

tDS

Setup time, data in (see Note 7)

5

5

5

ns

tRCS

Setup time, read command

0

0

0

ns

tCWL

Setup time, write command before CASx precharge

9

11

13

ns

tRWL

Setup time, write command before RASx precharge

10

12

14

ns

tWCS

Setup time, write command before CASx active

(early-write only)

0

0

0

ns

tWRP

Setup time, WEx high before RAS low (CBR refresh only)

12

12

12

ns

tWTS

Setup time, WEx low before RAS low (test mode only)

12

12

12

ns

tCSR

Setup time, CASx referenced to RASx ( CBR refresh only )

3

3

3

ns

tCAH

Hold time, column address

8

10

12

ns

tDH

Hold time, data in (see Note 7)

13

15

17

ns

tRAH

Hold time, row address

6

8

8

ns

tRCH

Hold time, read command referenced to CASx (see Note 8)

0

0

0

ns

tRRH

Hold time, read command referenced to RASx (see Note 8)

− 2

− 2

− 2

ns

tWCH

Hold time, write command during CASx active ( early-write only )

9

11

13

ns

tROH

Hold time, RASx referenced to OEx

8

10

10

ns

tWRH

Hold time, WEx high after RAS low (CBR refresh)

12

12

12

ns

tWTH

Hold time, WEx low after RAS low (test mode only)

12

12

12

ns

tCHR

Hold time, CASx referenced to RASx ( CBR refresh only )

8

8

8

ns

tOEH

Hold time, OEx command

14

16

19

ns

tRHCP

Hold time, RASx active from CASx precharge

33

40

45

ns

tAWD

Delay time, column address to write command ( read-write only )

47

54

62

ns

tCPW

Delay time, WEx low after CASx precharge (read-write only)

45

54

62

ns

tCRP

Delay time, CASx precharge to RASx

3

3

3

ns

tCWD

Delay time, CASx to write command ( read-write only )

35

39

45

ns

tOED

Delay time, OEx to data in

15

17

20

ns

tRAD

Delay time, RASx to column address (see Note 9)

8

20

10

25

10

30

ns

tRAL

Delay time, column address to RASx precharge

30

35

40

ns

tCAL

Delay time, column address to CASx precharge

20

23

28

ns

NOTES:

3. With ac parameters, it is assumed that tT = 2 ns.

6. In a read-write cycle, tRWD and tRWL must be observed.

7. Referenced to the later of CASx or WEx in write operations

8. Either tRCH or tRRH must be satisfied for a read cycle.

9. The maximum value is specified only to ensure access time.