TNETX3190 datasheet(54/66 Pages) TI1

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TNETX3190

ThunderSWITCH

™ 16/3 ETHERNET™ SWITCH

WITH 16 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS046B – FEBRUARY 1998 – REVISED APRIL 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

THxCLK

(input)

THxSYNC

(input)

THxCOL

THxCRS

THxLINK

THxRXD3–THxRXD0

THxRXDV

(inputs)

THxTXEN

THxTXD3–THxTXD0

THxRENEG

(outputs)

Figure 13. 10-Mbit/s Interface (Ports 00–15)

10-/100-Mbit/s MAC interface

Figures 14 and 15 show the timings at 100 Mbit/s and 10 Mbit/s for the 10-/100-Mbit/s port interfaces to the

TNETE2101 devices.

10-/100-Mbit/s receive ports (16, 17, and 18)

timing requirements (see Note 7 and Figure 14)†

NO.

MIN

MAX

UNIT

tc(MxxRCLK)

Cycle time, MxxRCLK

tw(MxxRCLKL)

Pulse duration, MxxRCLK low

tw(MxxRCLKH)

Pulse duration, MxxRCLK high

tsu(MxxRXD)

Setup time, MxxRXD3–MxxRXD0 valid before MxxRCLK

↑

tsu(MxxRXDV)

Setup time, MxxRXDV valid before MxxRCLK

↑

tsu(MxxRXER)

Setup time, MxxRXER valid before MxxRCLK

↑

th(MxxRXD)

Hold time, MxxRXD3–MxxRXD0 valid after MxxRCLK

↑

th(MxxRXDV)

Hold time, MxxRXDV valid after MxxRCLK

↑

th(MxxRXER)

Hold time, MxxRXER valid after MxxRCLK

↑

† xx = ports 16, 17, and 18

NOTE 7: Both MxxCRS and MxxCOL are driven asynchronously by the PHY. MxxRXD3–MxxRXD0 is driven by the PHY on the falling edge of

MxxRCLK. MxxRXD3–MxxRXD0 timing must be met during clock periods when MxxRXDV is asserted. MxxRXDV is asserted and

deasserted by the PHY on the falling edge of MxxRCLK. MxxRXER is driven by the PHY on the falling edge of MxxRCLK.

MxxRXD3–MxxRXD0

MxxRXDV

MxxRXER

(inputs)

MxxRCLK

(input)

Figure 14. 10-/100-Mbit/s Receive Ports

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