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RM48L930 bảng dữ liệu(PDF) 6 Page - Texas Instruments

tên linh kiện RM48L930
Giải thích chi tiết về linh kiện  RM48Lx30 16/32-Bit RISC Flash Microcontroller
PDF  147 Pages
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Trang chủ  http://www.ti.com
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RM48L930 bảng dữ liệu(HTML) 6 Page - Texas Instruments

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RM48L930
RM48L730
RM48L530
SPNS176
– SEPTEMBER 2011
www.ti.com
1
RM48Lx30 16/32-Bit RISC Flash Microcontroller
4.5
ARM© Cortex-R4F
™ CPU Information
............. 51
............................................................... 1
4.6
Clocks
.............................................. 54
1.1
Features
.............................................. 1
4.7
Clock Monitoring
.................................... 62
1.2
Applications
.......................................... 2
4.8
Glitch Filters
........................................ 64
4.9
Device Memory Map
................................ 65
1.3
Description
........................................... 3
4.10
Flash Memory
...................................... 72
1.4
Functional Block Diagram
............................ 5
4.11
Tightly-Coupled RAM Interface Module
............ 75
1.1
Device Configuration
................................. 7
4.12
Parity Protection for Accesses to peripheral RAMs
2
Device Package and Terminal Functions
......... 10
...................................................... 75
2.2
PGE QFP Package Pinout (144-Pin)
............... 10
4.13
On-Chip SRAM Initialization and Testing
........... 77
2.3
ZWT BGA Package Ball-Map (337 Ball Grid Array)
4.14
External Memory Interface (EMIF)
................. 79
...................................................... 11
4.15
Vectored Interrupt Manager
........................ 86
2.4
Terminal Functions
................................. 12
4.16
DMA Controller
..................................... 89
3
Device Operating Conditions
....................... 39
4.17
Real Time Interrupt Module
........................ 91
3.1
Absolute Maximum Ratings Over Operating
4.18
Error Signaling Module
............................. 93
Free-Air Temperature Range,
...................... 39
4.19
Reset / Abort / Error Sources
....................... 97
3.2
Device Recommended Operating Conditions
...... 39
4.20
Digital Windowed Watchdog
........................ 99
3.3
Switching Characteristics over Recommended
4.21
Debug Subsystem
................................. 100
Operating Conditions for Clock Domains
........... 40
5
Peripheral Information and Electrical
3.4
Wait States Required
............................... 40
Specifications
......................................... 111
3.5
Power Consumption Over Recommended
5.1
Peripheral Legend
................................. 111
Operating Conditions
............................... 41
5.2
Multi-Buffered 12bit Analog-to-Digital Converter
3.6
Input/Output Electrical Characteristics Over
..................................................... 111
Recommended Operating Conditions
.............. 42
5.3
General-Purpose Input/Output
.................... 120
3.7
Output Buffer Drive Strengths
...................... 42
5.4
Enhanced High-End Timer (N2HET)
.............. 121
3.8
Input Timings
....................................... 43
5.5
Controller Area Network (DCAN)
.................. 125
3.9
Output Timings
..................................... 43
5.6
Local Interconnect Network Interface (LIN)
....... 126
3.10
Low-EMI Output Buffers
............................ 45
5.7
Serial Communication Interface (SCI)
............ 127
4
System Information and Electrical Specifications
5.8
Inter-Integrated Circuit (I2C)
...................... 128
............................................................. 46
5.9
Multi-Buffered / Standard Serial Peripheral Interface
..................................................... 131
4.1
Device Power Domains
............................. 46
6
Mechanical Data
...................................... 143
4.2
Voltage Monitor Characteristics
.................... 47
6.1
Thermal Data
...................................... 143
4.3
Power Sequencing and Power On Reset
.......... 48
6.2
Packaging Information
............................ 143
4.4
Warm Reset (nRST)
................................ 50
6
Contents
Copyright
© 2011, Texas Instruments Incorporated
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