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TIBPLS506ACFN bảng dữ liệu(PDF) 6 Page - Texas Instruments

tên linh kiện TIBPLS506ACFN
Giải thích chi tiết về linh kiện  13 횞 97 횞 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
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MHz
fmax‡
CLK
ns
TIBPLS506AC
13
× 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
6
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITION
MIN
TYP†
MAX
UNIT
Without C-array
58
65
With C-array
33
45
External feedback without C-array
45
60
External feedback with C-array
R1 = 300
Ω,
28.5
40
Q (nonregistered)
R2 = 390
Ω,
6
25
tpd
Q (registered)
See Figure 5
3
10
I or Feedback
Q (nonregistered)
6
20
ns
ten
OE
↓
Q
1
6
10
ns
tdis
OE
↑
Q
1
6
10
ns
† All typical values are at VCC = 5 V, TA = 25°C.
‡ See the fmax calculations section.
fmax calculations
The following is a brief description of how the different operating frequencies can be achieved when using the
TIBPLS506A.
fmax without C-(complementary) array =
1
tsu ) tpd CLK to Q
where setup time tsu before CLK at the S/R
register inputs = 12 ns and propagation delay time tpd CLK to Q for the internal S/R registers = 5ns (difference
in tpd from CLK and feedback, 25 to 20).
Thus: fmax for this condition
+
1
(12 + 5) ns
+
1
17 ns
+ 58 MHz.
fmax with the C-array =
1
tsu ) tpd CLK to Q
where tsu setup time before CLK at the S/R register
inputs = 25 ns and propagation delay time tpd CLK to Q for the internal S/R registers = 5 ns (difference in tpd
from CLK and feedback, 25 to 20)
Thus: fmax for this condition
+
1
(25 + 5) ns
+
1
30 ns
+ 33 MHz.
fmax external feedback without the C-array =
1
tsu ) tpd CLK to Q
where setup time tsu before CLK at the
S/R register inputs = 12 ns and propagation delay time tpd CLK to Q for the internal S/R registers = 10 ns
Thus: fmax for this condition
+
1
(12 + 10) ns
+
1
22 ns
+ 45 MHz.
fmax external feedback with the C-array =
1
tsu ) tpd CLK to Q
where setup time tsu before CLK at the S/R
register inputs = 25 ns and propagation delay time tpd CLK to Q for the internal S/R registers = 10 ns.
Thus: fmax for this condition
+
1
(25 + 10) ns
+
1
35 ns
+ 28.5 MHz.



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