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DLPC100

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DLPS019B – DECEMBER 2009 – REVISED DECEMBER 2010

Projector Image Port Signal Sharing

Figure 2 illustrates the basic processing that occurs in the controller. The DLPC100 provides a single input port

for graphics and motion video inputs. The signals listed below support two input interface modes. Thus some

signals have different uses depending on the input interface mode being used.

Below are the two input image interface modes, signal descriptions, and pins needed on the DLPC100. describes

all the signals in the DLPC100.

•

BT.656, 9 pins

–

PDATA(7-0) – Projector Data

–

PCLK – Projector Clock (rising edge to capture input data)

•

Parallel Bus, 20 pins or 22 pins or 28 pins

–

PDATA(15-0) or PDATA(17-0) or PDATA(23-0) – Projector Data

–

HSYNC – Horizontal Sync

–

VSYNC – Vertical Sync

–

DATEN – Data En (active high)

–

PCLK – Projector Clock (rising edge, or falling edge, to capture input data)

by functional groups. Signals are referenced by names shown in the Pico Projector Formatter Reference

Schematic, TI drawing 2509552. The voltage characteristics of various I/O types are described in the I/O

Characteristics table.

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