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DAC1282IPW bảng dữ liệu(PDF) 14 Page - Texas Instruments |
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DAC1282IPW bảng dữ liệu(HTML) 14 Page - Texas Instruments |
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14 / 43 page ![]() 4-Bit Counter Reset D SYNC CLK CLK/16 Reset Digital Modulator SW/TD D Reset Current Generator Current Taps Tap Control Common-Mode Current Amplifier Summing Nodes AVDD VREF AVSS Sine Wave Table Digital Data Mux ... ... DAC1282 SBAS490 – DECEMBER 2011 www.ti.com The SYNC input synchronizes the output signal to a known time reference. In sine mode, SYNC resets the sine wave to the zero crossing. In Pulse mode, SYNC selects one of two user-programmed dc levels. The RESET/PWDN pin powers down the device when low. When RESET/PWDN is released high, the DAC1282 is reset. The SW/TD input is dual function. In digital data mode, the pin is the ones-density data input. In the other modes, SW/TD controls the opening/closing of the switch. Figure 33 shows the main details of the main DAC. The main DAC provides the digital-to-analog conversion by filtering the ones-density digital data. In operation, the current generator establishes the range current that is mirrored to a multi-tap, current-steering filter stage. The current generator is controlled by the analog gain control register that scales the weight of the tap currents to one of seven ranges (0 dB to –36 dB). The current-steering stage switches the tap currents to the positive or negative current summing nodes, as the digital input is sampled. A higher ones-density directs an increasing average current to one node than the other, thus increasing the differential current. The differential current is converted to differential voltage by the internal I/V converter stage. The common-mode current sources balance the current at the amplifier summing node. Figure 33. Main DAC Block Diagram 14 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): DAC1282 |
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