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DAC1282IPW bảng dữ liệu(PDF) 27 Page - Texas Instruments

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tên linh kiện DAC1282IPW
Giải thích chi tiết về linh kiện  LOW DISTORTION DIGITAL-TO-ANALOG CONVERTER FOR SEISMIC
PDF  43 Pages
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DAC1282IPW bảng dữ liệu(HTML) 27 Page - Texas Instruments

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−2
−1
0
1
2
−2
0
2
4
6
8
10
12
14
16
18
SYNC pin transition
Time (µs)
VOUTP, VOUTN
Pulse mode
Full Scale Step
G000
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
−50
0
50
100
150
200
250
300
350
400
450
SYNC pin transition
Time (µs)
(VOUTP − VOUTN)
Pulse Mode
Full scale step
G000
DAC1282
www.ti.com
SBAS490
– DECEMBER 2011
DC Noise
DC noise data are obtained using the DAC circuit of Figure 50 with data captured by the ADS1282. The noise is
measured in dc mode with the output voltage set to 0 V differential. The ADC gain is set to the complement of
the DAC gain for each output range. The noise is the standard deviation of 4096-point ADC acquisition record
(RMS noise, referred-to-output).
Total Harmonic Distortion (THD)
The DAC1282 achieves excellent THD performance. The THD data are obtained using the DAC circuit of
Figure 50 and captured by the ADS1282. The ADC gain is set to the complement of the DAC gain for each
output range.
THD is measured with a
–0.5-dBFS output signal level and a 31.25-Hz test frequency, then taking the FFT of the
4096-point ADC acquisition record. The ADC data points are increased to 16,384 for gains of 1/16, 1/32, and
1/64 for improved rendition of harmonics as a result of the higher noise floor. The THD measurement represents
the combination of the ADS1282 THD and the DAC1282 THD.
STEP RESPONSE
The step response of the DAC depends on the mode. In pulse mode, the DAC disables the external analog filter
formed by capacitors CAPP, CAPN. Disabling the analog filter in conjunction with the fast response pulse DAC
results in noticeably faster rise time and shorter settling time. Note that additional filter components in the signal
path may also affect the response time.
Figure 44 shows the pulse mode step response after the SYNC pin transition. Figure 45 shows the pulse mode
detail settling to 0.1% of final value after the SYNC pin transition.
Figure 44. Pulse Mode Step Response
Figure 45. Pulse Mode Step Response Detail
Copyright
© 2011, Texas Instruments Incorporated
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