AFE8220TPZPQ1 datasheet(11/49 Pages) TI1

tên linh kiện	AFE8220TPZPQ1

Giải thích chi tiết về linh kiện	DUAL INTERMEDIATE FREQUENCY (IF) ANALOG FRONT END FOR DIGITAL RADIO

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2C BUS INTERFACE

HIGH

LOW

SU_DAT

HD_DAT

STOP

START

SCK

SDA

BUF

2C Bus Interface Timing

AFE8220-Q1

www.ti.com....................................................................................................................................................... SBAS455A – JANUARY 2009 – REVISED JULY 2009

Figure 3. I2C Bus Interface Timing

PARAMETER

MIN

TYP

MAX

UNIT

fSCK

SCK clock frequency

400

kHz

VIL

Input voltage, low

0.3 × VDD

VIH

Input voltage, high

0.7 × VDD

tSTART

Setup time for START or repeated START condition

0.6

µs

tSTOP

Setup time for STOP condition

0.6

µs

tLOW

LOW period of SCK clock

1.3

µs

tHIGH

HIGH period of SCK clock

0.6

µs

100(1)

tHD_DAT

Data hold time from SCK falling

250

100(1)

tSU_DAT

Data setup time to SCK rising

250

tBUF

Bus free time between a STOP and START condition

4.7

µs

(1)

Valid when MCLK > 20 MHz; otherwise is 250 ns.

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