THS6204IPWPR datasheet(31/43 Pages) TI

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DIE

SideView(a)

EndView(b)

BottomView(c)

DIE

Thermal

Pad

THERMAL ANALYSIS

BOARD LAYOUT GUIDELINES

MaximumT =+85 C

+(0.955

32 C/W)=115.5 C

THS6204

www.ti.com ................................................................................................................................................... SBOS416C – OCTOBER 2007 – REVISED APRIL 2009

(1) The thermal pad is electrically isolated from all terminals in the package.

Figure 89. Views of Thermally-Enhanced PWP Package (Representative Only—Not to Scale)

Due to the high output power capability of the

Achieving

optimum

performance

with

THS6204, heatsinking or forced airflow may be

high-frequency amplifier like the THS6204 requires

required

under

extreme

operating

conditions.

careful attention to board layout parasitic and external

Maximum desired junction temperature sets the

component types. Recommendations that optimize

maximum allowed internal power dissipation as

performance include:

described below. In no case should the maximum

a) Minimize parasitic capacitance to any ac ground

junction temperature be allowed to exceed +130°C.

for all of the signal I/O pins. Parasitic capacitance on

Operating junction temperature (TJ) is given by TA +

the output and inverting input pins can cause

PD × θJA. The total internal power dissipation (PD) is

instability; on the noninverting input, it can react with

the sum of quiescent power (PDQ) and additional

the source impedance to cause unintentional band

power dissipation in the output stage (PDL) to deliver

limiting. To reduce unwanted capacitance, a window

load power. Quiescent power is the specified no-load

around the signal I/O pins should be opened in all of

supply current times the total supply voltage across

the ground and power planes around those pins.

the part. A PDL depends on the required output signal

Otherwise, ground and power planes should be

and load; using the previously developed model

unbroken elsewhere on the board.

described in the Total Driver Power for xDSL

Applications section, compute the maximum TJ using

b) Minimize the distance (< 0.25") from the

a THS6204 QFN-24 in the circuit of Figure 81

power-supply

pins

high-frequency

0.1

µF

operating

the

maximum

specified

ambient

decoupling capacitors. At the device pins, the ground

temperature of +85°C.

and power plane layout should not be in close

proximity to the signal I/O pins. Avoid narrow power

and ground traces to minimize inductance between

(19)

the

pins

and

the

decoupling

capacitors.

The

Although

this

still

well

below

the

specified

power-supply

connections

should

always

maximum junction temperature, system reliability

decoupled with these capacitors. An optional supply

considerations may require lower tested junction

decoupling capacitor across the two power supplies

temperatures.

The

highest

possible

internal

(for bipolar operation) improves second-harmonic

dissipation will occur if the load requires current to be

distortion performance. Larger (2.2

µF to 6.8µF)

forced into the output for positive output voltages or

decoupling capacitors, effective at lower frequency,

sourced from the output for negative output voltages.

should also be used on the main supply pins. These

This puts a high current through a large internal

can be placed somewhat farther from the device and

voltage drop in the output transistors. The output V-I

may be shared among several devices in the same

plot shown in the Typical Characteristics includes a

area of the PCB.

boundary for 1W maximum internal power dissipation

under these conditions.

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