73S8024RN-ILSLASHF datasheet(11/27 Pages) MAXIM

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DS_8024RN_020

73S8024RN Data Sheet

Rev. 2

The following steps show the activation sequence and the timing of the card control signals when the

system controller pulls the CMDVCC low while the RSTIN is high:

•

CMDVCC

is set low.

•

Next, the internal VCC control circuit checks the presence of VCC at the end of t1. In normal operation,

the voltage VCC to the card becomes valid during this time. If not, OFF goes low to report a fault to

the system controller, and the power VCC to the card is shut down.

•

Due to the fall of RSTIN at (t2), turn I/O (AUX1, AUX2) to reception mode.

•

CLK is applied to the card at the end of (t3), after I/O is in reception mode.

•

RST is to be a copy of RSTIN after (t4). RSTIN may be set high before t4, however the sequencer will

not set RST high until 42000 clock cycles after the start of CLK.

CMDVCC

VCC

I/O

CLK

RSTIN

t2 t3

RST

t1 = 0.510 ms (timing by 1.5MHz internal Oscillator)

t2 = 1.5µs, I/O goes to reception state

t3 = > 0.5µs, CLK active

t4 ≥ 42000 card clock cycles. Time for RST to become the copy of RSTIN

Figure 3: Activation Sequence – RSTIN High When CMDVCCB Goes Low

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