MPC8378E datasheet(87/128 Pages) FREESCALE

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MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

This figure shows the SerDes reference clock connection reference circuits for a single-ended clock driver.

It assumes the DC levels of the clock driver are compatible with device SerDes reference clock input’s DC

requirement.

Figure 62. Single-Ended Connection (Reference Only)

20.2.4

AC Requirements for SerDes Reference Clocks

The clock driver selected should provide a high quality reference clock with low phase noise and

cycle-to-cycle jitter. Phase noise less than 100 KHz can be tracked by the PLL and data recovery loops and

is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise

occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50

Ω to match the

transmission line and reduce reflections which are a source of noise to the system.

This table describes some AC parameters common to SGMII and protocols

Table 67. SerDes Reference Clock Common AC Parameters

At recommended operating conditions with XVDD_SRDS or XVDD_SRDS = 1.0 V ± 5%.

Parameter

Symbol

Min

Max

Unit

Note

Rising Edge Rate

Rise Edge Rate

1.0

4.0

V/ns

2, 3

Falling Edge Rate

Fall Edge Rate

1.0

4.0

V/ns

2, 3

Differential Input High Voltage

VIH

200

—

Differential Input Low Voltage

VIL

—

–200

n_REF_CLK

100

Ω differential PWB trace

SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

Single-Ended CLK

Driver Chip

Total 50

Ω. Assume clock driver’s

output impedance is about 16

Ω.

Chip

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