MMA6527KWR2 datasheet(4/56 Pages) FREESCALE

4 / 56 page

Sensor

Freescale Semiconductor, Inc.

MMA65xx

Pin Connections

Figure 5. Top View, 16-Pin QFN Package

VREGA

VSS

MOSI

SCLK

VCC

VSS

VREG

16 15 14 13

Table 2. Pin Descriptions

Name

Formal Name

Definition

1VREGA

Analog

Supply

This pin is connected to the power supply for the internal analog circuitry. An external capacitor must be

connected between this pin and VSSA. Reference Figure 1.

2VSS

Digital GND

This pin is the power supply return node for the digital circuitry.

3VREG

Digital

Supply

This pin is connected to the power supply for the internal digital circuitry. An external capacitor must be

connected between this pin and VSS. Reference Figure 1.

4VSS

Digital GND

This pin is the power supply return node for the digital circuitry.

ARM_Y/

PCM_Y

Y-Axis

Arm Output /

PCM Output

The function of this pin is configurable via the DEVCFG register as described in Section 3.1.6.6. When the

arming output is selected, ARM_Y can be configured as an open drain, active low output with a pullup current;

or an open drain, active high output with a pulldown current. Alternatively, this pin can be configured as a

digital output with PCM signal proportional to the Y axis acceleration data. Reference Section 3.8.10 and

Section 3.8.11. If unused, this pin must be left unconnected.

ARM_X/

PCM_X

X-Axis

Arm Output /

PCM Output

The function of this pin is configurable via the DEVCFG register as described in Section 3.1.6.6. When the

arming output is selected, ARM_X can be configured as an open drain, active low output with a pullup current;

or an open drain, active high output with a pulldown current. Alternatively, this pin can be configured as a

digital output with a PCM signal proportional to the X-axis acceleration data. Reference Section 3.8.10 and

Section 3.8.11. If unused, this pin must be left unconnected.

TEST /

VPP

Programming

Voltage

This pin provides the power for factory programming of the OTP registers. This pin must be connected to VSS

in the application.

MISO

SPI Data Out

This pin functions as the serial data output for the SPI port.

9VCC

Supply

This pin supplies power to the device. An external capacitor must be connected between this pin and VSS.

Reference Figure 1.

SCLK

SPI Clock

This input pin provides the serial clock to the SPI port. An internal pulldown device is connected to this pin.

MOSI

SPI Data In

This pin functions as the serial data input to the SPI port. An internal pulldown device is connected to this pin.

Chip Select

This input pin provides the chip select for the SPI port. An internal pullup device is connected to this pin.

VSSA

Analog GND

This pin is the power supply return node for analog circuitry.

No Connect

Not internally connected. This pin can be unconnected or connected to VSS in the application.

No Connect

Not internally connected. This pin can be unconnected or connected to VSS in the application.

VSSA

Analog GND

This pin is the power supply return node for analog circuitry.

PAD

Die Attach

Pad

This pin is the die attach flag, and is internally connected to VSS. Reference Section 5 for die attach pad

connection details.

Corner Pads

The corner pads are internally connected to VSS.

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