LTM4613 datasheet(8/20 Pages) LINER

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LTM8048

8048fa

PIN FUNCTIONS

VOUT1 (Bank 1): VOUT1 and VOUT– comprise the isolated

output of the LTM8048 flyback stage. Apply an external

capacitor between VOUT1 and VOUT–. Do not allow VOUT–

to exceed VOUT1.

VOUT– (Bank 2): VOUT– is the return for both VOUT1 and

VOUT2. VOUT1 and VOUT– comprise the isolated output of

the LTM8048. In most applications, the bulk of the heat

flow out of the LTM8048 is through the GND and VOUT–

pads, so the printed circuit design has a large impact on

the thermal performance of the part. See the PCB Layout

and Thermal Considerations sections for more details.

Apply an external capacitor between VOUT1 and VOUT–.

VOUT2 (Bank 3): The output of the secondary side linear

post regulator. Apply the load and output capacitor between

VOUT2 and VOUT–. See the Applications Information section

for more information on output capacitance and reverse

output characteristics.

GND (Bank 4): This is the primary side local ground of the

LTM8048 primary. In most applications, the bulk of the heat

flow out of the LTM8048 is through the GND and VOUT–

pads, so the printed circuit design has a large impact on

the thermal performance of the part. See the PCB Layout

and Thermal Considerations sections for more details.

VIN (Bank 5): VIN supplies current to the LTM8048’s inter-

nal regulator and to the integrated power switch. These

pins must be locally bypassed with an external, low ESR

capacitor.

ADJ2 (pin A2): This is the input to the error amplifier of the

secondary side LDO post regulator. This pin is internally

clamped to ±7V. The ADJ2 pin voltage is 1.22V referenced

to VOUT– and the output voltage range is 1.22V to 12V. Ap-

ply a resistor from this pin to VOUT–, using the equation

RADJ2 = 608.78/(VOUT2 – 1.22)kΩ. If the post regulator

is not used, leave this pin floating.

BYP (Pin B2): The BYP pin is used to bypass the refer-

ence of the LDO to achieve low noise performance from

the linear post regulator. The BYP pin is clamped internally

to ±0.6V relative to VOUT–. A small capacitor from VOUT2

to this pin will bypass the reference to lower the output

voltage noise. A maximum value of 0.01μF can be used

for reducing output voltage noise to a typical 20μVRMS

over a 100Hz to 100kHz bandwidth. If not used, this pin

must be left unconnected.

RUN (Pin F3): A resistive divider connected to VIN and this

pin programs the minimum voltage at which the LTM8048

will operate. Below 1.24V, the LTM8048 does not deliver

power to the secondary. Above 1.24V, power will be de-

livered to the secondary and 10μA will be fed into the SS

pin. When RUN is less than 1.24V, the pin draws 2.5μA,

allowing for a programmable hysteresis. Do not allow a

negative voltage (relative to GND) on this pin.

ADJ1 (Pins G7): Apply a resistor from this pin to GND to

set the output voltage VOUT1 relative to VOUT–, using the

recommended value given in Table 1. If Table 1 does not

list the desired VOUT1 value, the equation

RADJ1 = 28.4 VOUT1

–0.879

()kΩ

may be used to approximate the value. To the seasoned

designer, this exponential equation may seem unusual. The

equation is exponential due to non-linear current sources

that are used to temperature compensate the regulation.

BIAS (Pin H5): This pin supplies the power necessary to

operate the LTM8048. It must be locally bypassed with a

low ESR capacitor of at least 4.7μF. Do not allow this pin

voltage to rise above VIN.

SS (Pin H6): Place a soft-start capacitor here to limit inrush

current and the output voltage ramp rate. Do not allow a

negative voltage (relative to GND) on this pin.

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