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LT5514 bảng dữ liệu(PDF) 6 Page - Linear Technology |
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LT5514 bảng dữ liệu(HTML) 6 Page - Linear Technology |
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6 / 24 page ![]() LTC2201 6 2201f TIMING CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND, with GND and OGND shorted (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3.3V, fSAMPLE = 20MHz, input range = 2.5VP-P with differential drive (PGA = 0), unless otherwise specified. Note 5: Integral nonlinearity is defined as the deviation of a code from a “best fit straight line” to the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from – 1/2LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2’s complement output mode. Note 7: Guaranteed by design, not subject to test. Note 8: Recommended operating conditions. Note 9: Dynamic current from switched capacitor inputs is large compared to DC leakage current, and will vary with sample rate. Note 10: Leakage current will experience transient at power up. Keep resistance < 1kΩ. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD Analog Supply Voltage l 3.135 3.3 3.465 V PSHDN Shutdown Power SHDN = VDD, CLK = VDD 2mW OVDD Output Supply Voltage l 0.5 3.6 V IVDD Analog Supply Current l 64 80 mA PDIS Power Dissipation l 211 264 mW POWER REQUIREMENTS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fS Sampling Frequency l 1 20 MHz tL CLK Low Time Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 20 5 25 25 500 500 ns ns tH CLK High Time Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 20 5 25 25 500 500 ns ns tAP Sample-and-Hold Aperture Delay 0.9 ns tD CLK to DATA Delay CL = 5pF (Note 7) l 1.3 3.1 4.9 ns tC CLK to CLKOUT Delay CL = 5pF (Note 7) l 1.3 3.1 4.9 ns tSKEW DATA to CLKOUT Skew CL = 5pF (Note 7) l –0.6 0 0.6 ns DATA Access Time Bus Relinquish Time CL = 5pF (Note 7) (Note 7) l l 5 5 15 15 ns ns Pipeline Latency 7 Cycles |
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