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LT5514 bảng dữ liệu(PDF) 18 Page - Linear Technology

tên linh kiện LT5514
Giải thích chi tiết về linh kiện  16-Bit, 20Msps ADC
PDF  24 Pages
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LT5514 bảng dữ liệu(HTML) 18 Page - Linear Technology

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LTC2201
18
2201f
Digital Output Randomizer
Interference from the ADC digital outputs is sometimes
unavoidable. Interference from the digital outputs may be
from capacitive or inductive coupling or coupling through
the ground plane. Even a tiny coupling factor can result in
discernible unwanted tones in the ADC output spectrum.
By randomizing the digital output before it is transmitted
off chip, these unwanted tones can be randomized, trading
a slight increase in the noise floor for a large reduction in
unwanted tone amplitude.
The digital output is “Randomized” by applying an exclu-
sive-OR logic operation between the LSB and all other data
output bits. To decode, the reverse operation is applied;
that is, an exclusive-OR operation is applied between the
LSB and all other bits. The LSB, OF and CLKOUT output
are not affected. The output Randomizer function is active
when the RAND pin is high.
CLKOUT
OF
D15/D0
D14/D0
D2/D0
D1/D0
D0
D0
D1
RAND = HIGH,
SCRAMBLE
ENABLED
D2
D14
D15
OF
CLKOUT
RAND
2201 F10
LTC2201
Figure 10. Functional Equivalent of Digital Output Randomizer
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven. For
example, if the converter is driving a DSP powered by a
1.8V supply, then OVDD should be tied to that same 1.8V
supply. In CMOS mode OVDD can be powered with any
logic voltage up to 3.6V. OGND can be powered with any
voltage from ground up to 1V and must be less than OVDD.
The logic outputs will swing between OGND and OVDD.
APPLICATIONS INFORMATION
Figure 11. Descrambling a Scrambled Digital Output
D1
D0
D2
D14
D15
PC BOARD
FPGA
CLKOUT
OF
D15/D0
D14/D0
D2/D0
D1/D0
D0
2201 F11
LTC2201



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