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tên linh kiện SLA24C01-S/P
Giải thích chi tiết về linh kiện  1/2 Kbit 128/256 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus
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SLx 24C01/02/P
Semiconductor Group
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1998-07-27
6.2
Current Address Read
The EEPROM content is read without setting an EEPROM address, in this case the
current content of the address counter will be used (e.g. to continue a previous read
operation after the Master has served an interrupt).
Figure 12
Current Address Read
Transmission of CSR
For a current address read the master generates a START
condition, which is followed by the command byte CSR (chip
select read). The receipt of the CSR-byte is acknowledged by
the EEPROM with a low on the SDA line.
Transmission of
EEPROM Data
During the next eight clock pulses the EEPROM transmits the
data byte and increments the internal address counter.
STOP Condition from
Master
During the following clock cycle the masters releases the bus
and then transmits the STOP condition.
Command Byte
CSR
S
P
A
C
K
S
T
A
R
T
T
P
O
S
Bus Activity
Master
SDA Line
Bus Activity
EEPROM
IED02132
Data Byte
1



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