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SLA24C01-S/P bảng dữ liệu(PDF) 15 Page - Siemens Semiconductor Group

tên linh kiện SLA24C01-S/P
Giải thích chi tiết về linh kiện  1/2 Kbit 128/256 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus
PDF  27 Pages
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nhà sản xuất  SIEMENS [Siemens Semiconductor Group]
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SLx 24C01/02/P
Semiconductor Group
15
1998-07-27
6
Read Operations
Reading of the EEPROM data is initiated by the Master with the command byte CSR.
6.1
Random Read
Random read operations allow the master to access any memory location.
Figure 11
Random Read
Address Setting
The master generates a START condition followed by the
command byte CSW. The receipt of the CSW-byte is
acknowledged by the EEPROM with a low on the SDA line.
Now the master transmits the EEPROM address (EEA) to the
EEPROM and the internal address counter is loaded with the
desired address.
Transmission of CSR
After the acknowledge for the EEPROM address is received,
the master generates a START condition, which terminates
the initiated write operation. Then the master transmits the
command byte CSR for read, which is acknowledged by the
EEPROM.
Transmission of
EEPROM Data
During the next eight clock pulses the EEPROM transmits the
data byte and increments the internal address counter.
STOP Condition from
Master
During the following clock cycle the masters releases the bus
and then transmits the STOP condition.
Command Byte
CSW
S
P
A
C
K
C
K
A
S
T
A
R
T
T
P
O
S
EEPROM Address
EEA n
Bus Activity
Master
SDA Line
Bus Activity
EEPROM
IED02133
C
K
A
Data Byte
1
0
S
T
R
A
T
S
CSR
Command Byte



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