TLC5948APWPR datasheet(39/50 Pages) TI1

39 / 50 page

2 A, 10 A, 20

or 1 mA

OUT Current for IDM

'0'

257-Bit Common Shift

(Internal)

SID Loaded Into Common Shift Register

GS Data

LAT

'1'

LOD

XXXXh

LOD

XXXXh

LOD

0000h

LOD

XXXXh

LOD data are not stable immediately after OUT turn on.

LOD and LSD Data Latch

(Internal)

16-Bit LOD and LSD

Circuit Output Data

(Internal)

LOD and LSD Old Data

LOD

XXXXh

0 A

LOD/LSD

0000h

LOD

XXXXh

0 A

2 A, 10 A, 20

LOD and LSD data latch updated with latest

data at the clock time selected by LATTMG bit.

OUT Current

for PWM Control

(GSDATA = FFFFh)

0 mA

(2)

Programmed

Output Current

BLANK Bit

in Control Data Latch

(Internal)

2 3

16 17 18 19 20

65533 65535

65534 65536

LOD

XXXXh

Control Data

Unknown

'1'

TMGRST Bit

in Control Data Latch

(Internal)

(1)

Internal BLANK is generated when the LAT

signal is input because display timing reset is enabled.

Control data write

latch signal.

GS data write latch signal.

(3)

TLC5948A

www.ti.com

SBVS192 – MARCH 2012

(1) Set the current with the external resistor and DC and BC data.

(2) Select the output current with the IDMCUR bit in the control data latch.

(3) Select clock time with the LATTMG bit in the control data latch.

Figure 35. PWM Operation Timing

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