CDCUN1208LP

SCAS928 – MAY 2012

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Table 11. CDCUN1208LP Registers 11–15 Bit Definitions

REGISTER

POWER UP

RAM BIT

BIT NAME

RELATED BLOCK

DESCRIPTION / FUNCTION

Address

CONDITION

15

TI RESERVED

14

TI RESERVED

13

TI RESERVED

12

TI RESERVED

11

TI RESERVED

10

TI RESERVED

9

TI RESERVED

8

TI RESERVED

0

7

TI RESERVED

0

6

TI RESERVED

0

5

IN_DIV[1]

Input Divider Control

0

1 1 = /8

11

Input

1 0 = /4

(IN2 – Divider)

4

IN_DIV[0]

0

0 1 = /2

0 0 = /1

3

IN_TYPE[1]

Input Type

0

1 1 = HCSL

1 0 = LVCMOS

(IN1 and IN2 Type)

2

IN_TYPE[0]

0

0 1 = LVCMOS

0 0 = LVDS

1

INSEL[1]

Input Multiplexer Control

0

1 1 = Control via INSEL pin

Input

1 0 = Smart MUX Enabled, IN

1=Primary

(Multiplexer)

0

INSEL[0]

0

0 1 = IN2 Buffer Selected

0 0 = IN1 Buffer Selected

12-14

ALL

TI RESERVED

2-15

TI RESERVED

Device Reset

1

RESET

1 = Reset Device

0

15

0 = Run Device

Device Power Down

0

PD

1 = Device is powered down

0

0 = Device is active

(1)

When configuring device inputs as LVCMOS, apply the signal-ended clock signal to INxP and leave INxN either floating or ground it.

mode.

28

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