DM9302EP datasheet(17/64 Pages) DAVICOM

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DM9302

10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus

Preliminary datasheet

DM9302-15-DS-P01

July 30, 2009

Key to Default

In the register description that follows, the default column

takes the form:

Where:

<Reset Value>:

Bit set to logic one

Bit set to logic zero

No default value

P = power on reset, by PWRST# pin, default value

H = hardware reset, by Reg. 52H bit 6, default value

S = software reset, by Reg. 00H bit 0, default value

E = default value from EEPROM setting

T = default value from strap pin

<Access Type>:

RO = Read only

RW = Read/Write

R/C = Read and Clear

RW/C1=Read/Write and Cleared by write 1

WO = Write only

Reserved bits should be written with 0.

Reserved bits are undefined on read access.

6.1 Network Control Register (00H)

Bit

Name

Default

Description

RESERVED

0,RO

Reserved

LNK_X_EN

PH0,RW

Link Change Status Enable

When set, it enables to report port 0 or 1 link change status function. Clearing this

bit will also clear link change status

This bit will not be affected after a software reset

CLR1

PH0,RW

0: REG. 01H auto-cleared after read

1: REG. 01H cleared by writing 1 to respected bit.

4:2

RESERVED

0,RO

Reserved

LBK

PH0,

Loopback test Mode

All transmit packets from processor port are forward to processor port itself.

RST

PH0,RW

Software reset and auto clear after 10us

6.2 Network Status Register (01H)

Bit

Name

Default

Description

7:6

RESERVED

0,RO

Reserved

LINK_X_ST

PH0,

W/C1

Link Change Status.

This bit is set after port 0 or 1 link changed.

If bit 5 of NCR is set, this bit is cleared by write 1; Otherwise it can be cleared by

read or write 1.

RESERVED

0,RO

Reserved

TX2END

PHS0,

RW/C1

TX Packet 2 Complete Status.

This bit is set after transmit completion of packet index 2

If bit 5 of NCR is set, this bit is cleared by write 1; Otherwise it can be cleared by

read or write 1.

TX1END

PHS0,

RW/C1

TX Packet 1 Complete status.

This bit is set after transmit completion of packet index 1

If bit 5 of NCR is set, this bit is cleared by write 1; Otherwise it can be cleared by

read or write 1.

1:0

RESERVED

0,RO

Reserved

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