DM9302EP datasheet(43/64 Pages) DAVICOM

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DM9302

10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus

Preliminary datasheet

DM9302-15-DS-P01

July 30, 2009

8.8 DAVICOM Specified Configuration Register (DSCR) – 10H

Bit

Bit Name

Default

Description

BP_4B5B

0,RW

Bypass 4B5B Encoding and 5B4B Decoding

1 = 4B5B encoder and 5B4B decoder function bypassed

0 = Normal 4B5B and 5B4B operation

BP_SCR

0, RW

Bypass Scrambler/Descrambler Function

1 = Scrambler and descrambler function bypassed

0 = Normal scrambler and descrambler operation

BP_ALIGN

0, RW

Bypass Symbol Alignment Function

1 = Receive functions (descrambler, symbol alignment and symbol

decoding functions) bypassed. Transmit functions (symbol

encoder and scrambler) bypassed

0 = Normal operation

BP_ADPOK

0, RW

BYPASS ADPOK

Force signal detector (SD) active. This register is for debug only,

not release to customer

1: Forced SD is OK,

0: Normal operation

Reserved

Force to 0 in application

1, RW

100BASE-TX Mode Control

1 = 100BASE-TX operation

0 = 100BASE-FX operation

Reserved

0, RO

Reserved

0, RW

Reserved

F_LINK_100

0, RW

Force Good Link in 100Mbps

1 = Force 100Mbps good link status

0 = Normal 100Mbps operation

This bit is useful for diagnostic purposes

Reserved

0, RW

Reserved

Force to 0 in application.

COL_LED

0, RW

COL LED Control (valid in PHY test mode)

RPDCTR-EN

1, RW

Reduced Power Down Control Enable

This bit is used to enable automatic reduced power down

1 = Enable automatic reduced power down

0 = Disable automatic reduced power down

SMRST

0, RW

Reset State Machine

When writes 1 to this bit, all state machines of PHY will be reset.

This bit is self-clear after reset is completed

MFPSC

1, RW

MF Preamble Suppression Control

MII frame preamble suppression control bit

1 = MF preamble suppression bit on

0 = MF preamble suppression bit off

SLEEP

0, RW

Sleep Mode

Writing a 1 to this bit will cause PHY entering the Sleep mode and

power down all circuit except oscillator and clock generator circuit.

When waking up from Sleep mode (write this bit to 0), the

configuration will go back to the state before sleep; but the state

machine will be reset

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