ADIS16136SLASHPCBZ datasheet(12/20 Pages) AD

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ADIS16136

Data Sheet

Rev. A | Page 12 of 20

AVERAGING/DECIMATION FILTER

The DEC_RATE register (see Table 18) provides user control

for the final filter stage (see Figure 18), which averages and

decimates the output data. For systems that value lower sample

rates, this filter stage provides an opportunity to lower the sample

rate while maintaining optimal bias stability performance. The

−3 dB bandwidth of this filter stage is approximately one half

the output data rate. For example, set DEC_RATE[7:0] = 0x04

(DIN = 0xA204) to reduce the sample rate by a factor of 16.

When the factory default 1024 SPS sample rate is used, this

decimation setting reduces the output data rate to 64 SPS and

the sensor bandwidth to approximately 32 Hz.

Table 18. DEC_RATE Bit Descriptions

Bits

Description (Default = 0x0000)

[15:5]

Don’t care

[4:0]

Binary; D variable in Figure 18; maximum = 10000 (16)

Figure 18. Sampling and Frequency Response Block Diagram

MEMS

GYRO

410Hz

1595Hz

CLOCK

CLKIN

÷ND

–3dB BANDWIDTH = 380Hz

B = AVG_CNT[2:0]

NB = 2B

NT = 2NB – 1

NT = TOTAL NUMBER OF TAPS

SP ≥ 15

SP = SMPL_PRD

D = DEC_RATE[4:0]

ND = 2D

ND = NUMBER OF TAPS

ND = DATA RATE DIVISOR

fS =

32,768

SP + 1

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